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參數(shù)資料
| 型號： | AM79C970 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線 |
| 文件頁數(shù)： | 39/168頁 |
| 文件大小： | 943K |
| 代理商： | AM79C970 |
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AMD
P R E L I M I N A R Y
1-906
Am79C970
It is not necessary for the software to insure that the
buffer address pointer contained in descriptor word 0
matches the address restrictions given in the table. If the
buffer pointer does not meet the conditions set forth in
the table, then the PCnet-PCI controller will simply post-
pone the start of linear bursting until enough non-burst
FIFO DMA transfers have been performed to bring the
current working buffer pointer value to a valid linear
burst starting address. This operation is referred to as
aligning the buffer address to a valid linear burst starting
address. Once this has been done, the PCnet-PCI con-
troller will recognize that the address for the current ac-
cess is a valid linear burst starting address, and it will
automatically begin to perform linear burst accesses at
that time, provided of course that the software has en-
abled the linear burst mode.
Note that if the software would provide only valid linear
burst starting addresses in the buffer pointer, then the
PCnet-PCI controller could avoid performing the align-
ment operation. It would begin linear burst accesses on
the very first of the buffer transfers thereby allowing a
slight gain in bus bandwidth efficiency.
Linear Burst DMA Address Alignment
Linear bursting may begin during a bus mastership pe-
riod which was initially performing only non-burst
operations. A change from non-burst operation to linear
bursting will normally occur during linear burst DMA ad-
dress alignment operations.
If the PCnet-PCI controller is programmed for burst
mode (i.e. BREADE and/or BWRITE bits of BCR18 are
set to ONE), and the PCnet-PCI controller requests the
bus, but the starting address of the first transaction does
not meet the conditions as specified in the table above,
then the PCnet-PCI controller will perform non-burst ac-
cesses until it arrives at an address that does meet the
conditions described in the table. At that time, and with-
out releasing the bus, the PCnet-PCI controller will in-
voke the linear burst mode.
Figure 16 shows an example of a linear burst DMA align-
ment operation being performed. The first access to the
transmit buffer is in non-burst mode, because the cur-
rent address does not align with a linear burst boundary.
The PCnet-PCI controller switches to burst mode begin-
ning with the second transfer.
REQ
stays asserted dur-
ing all transfers.
18220C-18
FRAME
CLK
AD
IRDY
TRDY
C/
BE
DEVSEL
REQ
GNT
1
2
3
4
5
6
7
8
n0Ch
0000
0110
11
10
9
PAR
PAR
DATA
n10h
DATA
DATA
PAR
PAR
PAR
DEVSEL
is sampled by the PCnet-PCI controller.
0000
1110
Figure 16.
Burst Alignment
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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