參數(shù)資料
型號： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù)： 17/168頁
文件大?。?/td> 943K
代理商： AM79C970
AMD
P R E L I M I N A R Y
1-884
Am79C970
When
RST
is active, NAND tree testing is enabled. All
PCI interface pins are in input mode. The result of the
NAND tree testing can be observed on the NOUT output
(pin 62).
SERR
System Error
Input/Output
This signal is asserted for one CLK by the PCnet-PCI
controller when it detects a parity error during the ad-
dress phase when its AD[31:00] lines are inputs.
The
SERR
pin is only active when SERREN (bit 8) and
PERREN (bit 6) in the PCI command register are set.
When
RST
is active,
SERR
is an input for NAND tree
testing.
STOP
Stop
Input/Output
In the slave role, the PCnet-PCI controller drives the
STOP
signal to inform the bus master to stop the current
transaction. In the bus master role, the PCnet-PCI con-
troller receives the
STOP
signal and stops the current
transaction.
When
RST
is active,
STOP
is an input for NAND tree
testing.
TRDY
Target Ready
Input/Output
This signal indicates that the PCnet-PCI controllers abil-
ity as a selected device to complete the current data
phase of the transaction.
TRDY
is used in conjunction
with the
IRDY
. A data phase is completed on any clock
both
TRDY
and
IRDY
are asserted. During a read
TRDY
indicates that valid data is present on AD[31:00]. During
a write,
TRDY
indicates that data has been accepted.
Wait states are inserted until both
IRDY
and
TRDY
are
asserted simultaneously.
When
RST
is active,
TRDY
is an input for NAND tree
testing.
Board Interface
LED1
LED1
Output
This pin is shared with the EESK function. As
LED1
, the
function and polarity of this pin are programmable
through BCR5. By default,
LED1
is active LOW and it in-
dicates receive activity on the network. The
LED1
output
from the PCnet-PCI controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
The
LED1
pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present
at the PCnet-PCI controller Microwire interface. At the
trailing edge of the
RST
pin,
LED1
is sampled to deter-
mine the value of the EEDET bit in BCR19. A sampled
HIGH value means that an EEPROM is present, and
EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection sec-
tion for more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in or-
der to resolve the EEDET setting.
LED3
LED3
Output
This pin is shared with the EEDO function. When func-
tioning as
LED3
, the signal on this pin is programmable
through BCR7. By default,
LED3
is active LOW and it in-
dicates transmit activity on the network. Special atten-
tion must be given to the external circuitry attached to
this pin. If an LED circuit were directly attached to this
pin, it would create an I
OL
requirement that could not be
met by the serial EEPROM that would also be attached
to this pin. (This pin is multifunctioned with the EEDO
function of the Microwire serial EEPROM interface.)
Therefore, if this pin is to be used as an additional LED
output while an EEPROM is used in the system, then
buffering is required between the
LED3
pin and the LED
circuit. If no EEPROM is included in the system design,
then the
LED3
signal may be directly connected to an
LED without buffering. The
LED3
output from the
PCnet-PCI controller is capable of sinking the neces-
sary 12 mA of current to drive an LED in this case. For
more details regarding LED connection, see the section
on LEDs.
LNKST
LINK Status
Output
This pin provides 12 mA for driving an LED. By default, it
indicates an active link connection on the 10BASE-T in-
terface. This pin can also be programmed to indicate
other network status (see BCR4). The
LNKST
pin polar-
ity is programmable, but by default, it is active LOW.
Note that this pin is multiplexed with the EEDI function.
SLEEP
Sleep
Input
When
SLEEP
is asserted (active LOW), the PCnet-PCI
controller performs an internal system reset of the
S_RESET type and then proceeds into a power savings
mode. (The reset operation caused by
SLEEP
assertion
will not affect BCR registers.) The PCI interface section
is not effected by
SLEEP
. In particular, access to the
PCI configuration space remains possible. None of the
相關(guān)PDF資料
PDF描述
AM79C971VCW PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C971 PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*