參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 115/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
47 of 172
Table 8-6 MAC Control Registers
Address
Register
Register Description
0000h-0003h
SU.MACCR
MAC Control Register. This register is used for
programming full duplex, half duplex, promiscuous mode,
and back-off limit for half duplex. The transmit and receive
enable bits must be set for the MAC to operate.
0004h-0007h
SU.MACAH
MAC Address High Register. This provides the physical
address for this MAC.
0008h-000Bh
SU.MACAL
MAC Address Low Register. This provides the physical
address for this MAC.
0014h-0017h
SU.MACMIIA
MII Address Register. The address for PHY access
through the MDIO interface.
0018h-001Bh
SU.MACMIID
MII Data Register. Data to be written to (or read from) the
PHY through MDIO interface.
001Ch-001Fh
SU.MACFCR
Flow Control Register
0100h-0103h
SU.MMCCTRL
MMC Control Register bit 0 for resetting the status
counters
Table 8-7 MAC Status Registers
Address
Register
Register Description
0200h-0203h
SU.RxFrmCntr
All Frames Received counter
0204h-0207h
SU.RxFrmOKCtr
Number of Received Frames that are Good
0300h-0303h
SU.TxFrmCtr
Number of Frames Transmitted
0308h-030Bh
SU.TxBytesCtr
Number of Bytes Transmitted
030Ch-030Fh
SU.TxBytesOkCtr
Number of Bytes Transmitted with good frames
0334h-0337h
SU.TxFrmUndr
Transmit FIFO underflow counter
0338h-033Bh
SU.TxBdFrmsCtr
Transmit Number of Frames Aborted
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