Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely e" />
參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 82/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
172 of 172
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor
product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any
time.
Maxim Integrated Products, 120 San Ga briel Drive, Sunnyvale, CA 94086 408-737-7600
2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
14 REVISION HISTORY
REVISION
DESCRIPTION
021805
New Product Release.
030106
Added TCLKI to TSER Output Delay Minimum of 3ns.
Added TCLKI to TBSYNC Setup Time Minimum of 3.5ns.
Corrected typo in Table 8-9, Transmit Queue High Threshold entry.
Clarified definition of GL.IDR.ID5-7.
Added definition for BPCLR.PLF[4:0].
Corrected ball assignment shown in the SDATA[3] pin listing for the 100-pin CSBGA package.
Corrected pin description of MDC.
Corrected default value listed in the SU.RMFSRL register definition.
Added Figure 8-11, HDLC Encapsulation of MAC Frame.
Corrected FULLDS pin description for Hardware Mode.
Corrected SU.MACCR.DRO bit description.
Clarified pin description of RMIIMIIS
Clarified pin description of FULLDS
Clarified pin description of H10S
Clarified RMIIMIIS, FULLDS, and H10S internal ties in the 100 pin package.
Clarified Hardware Mode operation with MODEC[1:0] = 10.
Added power supply sequence to the Example Device Initialization Sequence.
Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC register definitions.
Clarified the GL.C1QPR register definition.
Clarified the 169 Pin package outline drawing and added side view.
Added SU.MACCR.PM and SU.MACCR.PAM bit definitions.
122006
Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC registers to the
register bit map.
Corrected pin description of RST.
Corrected pin description of REF_CLK
Clarified text regarding use of REF_CLKO in DCE and RMII modes.
Corrected SU.GCR.H10S bit definition.
Corrected the SU.RQLT and SU.RQHT default values to zero.
Clarified section 8.18 on X.86 mode synchronization.
Corrected value of “Receiver Maximum Frame Size” listed in Table 8-9.
Corrected low-power mode information in Section 8.4.
Added D/C operating current maximum values.
Updated D/C operating current typical values.
Added D/C Characteristic entries for Supply currents in “standby” conditions.
Updated package drawings.
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