參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 79/172頁
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
17 of 172
7 PIN DESCRIPTIONS
7.1 Pin Functional Description
Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns. JTAG pins are not available on the Hardware mode/SPI-only DS33ZH11 (10mm CSBGA)
Note: I = Input; O = Output; Ipu = Input, with pullup; Oz = Output, with tri-state; IO = Bidirectional pin; IOz = Bidirectional pin, with tri-state
Table 7-1 Detailed Pin Descriptions
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
SERIAL INTERFACE IO PINS
TCLKI
F1
B1
I
Serial Interface Transmit Clock Input: The clock
reference for TSER, which is output on the rising edge of
the clock. TCLKI supports gapped clocking, up to a
maximum frequency of 52 MHz.
TSER
F2
A2
O
Transmit Serial Data Output: Output on the rising edge
of TCLKI. Selective clock periods can be skipped for
output of TSER dependent on the TDEN settings or
gapped clock input (TCLKI). The maximum data rate is 52
Mbps.
TDEN/
TBSYNC
F5
—
IO
Transmit Data Enable (Input): The transmit data enable
is programmable to selectively block/enable the transmit
data. The TDEN signal must occur one clock edge prior to
the affected data bit. The active polarity of TDEN is
programmable in register LI.TSLCR. It is recommended
for both T1/E1 and T3/E3 applications that use gapped
clocks. The TDEN signal is provided for interfacing to
framers that do not have a gapped clock facility.
Transmit Byte Sync (Output): This output can be used
by an external Serial to Parallel to convert TSER stream to
byte wide data. This output indicates the last bit of the
byte data sent serially on TSER. This signal is only active
in the X.86 Mode.
Note that while in Hardware mode with HDLC (non X.86)
operation, this pin must be tied high.
RCLKI
G2
B2
I
Serial Interface Receive Clock Input: Reference clock
for receive serial data on RSER. Gapped clocking is
supported, up to the maximum RCLKI frequency of 52
MHz.
RSER
H1
B3
I
Receive Serial Data Input: Receive Serial data arrives on
the rising edge of the clock.
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