參數(shù)資料
型號: DS33ZH11+
廠商: Maxim Integrated Products
文件頁數(shù): 153/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應用: 數(shù)據(jù)傳輸
接口: 串行
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 100-LFBGA,CSPBGA
供應商設備封裝: 100-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33Z11 Ethernet Mapper
81 of 172
Register Name:
GL.SDMODE1
Register Description:
Global SDRAM Mode Register 1
Register Address:
3Ah
Bit #
7
6
5
4
3
2
1
0
Name
-
WT
BL2
BL1
BL0
Default
0
1
Bit 3: Wrap Type (WT) This bit is used to configure the wrap mode.
0 = Sequential
1 = Interleave
Bits 0- 2: Burst Length 0 through 2 (BL0 – BL2) These bits are used to determine the Burst Length.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
GL.SDMODE2
Register Description:
Global SDRAM Mode Register 2
Register Address:
3Bh
Bit #
7
6
5
4
3
2
1
0
Name
-
LTMOD2
LTMOD1
LTMOD0
Default
0
1
0
Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency
Note: Only CAS Latency of 2 or 3 is allowed
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
GL.SDMODEWS
Register Description:
Global SDRAM Mode Register Write Status
Register Address:
3Ch
Bit #
7
6
5
4
3
2
1
0
Name
-
SDMW
Default
0
Bit 0: SDRAM Mode Write (SDMW) Setting this bit to 1 will write the current values of the mode control and
refresh time control registers to the SDRAM. The user must clear this bit and set it again for subsequent write
operations.
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