參數(shù)資料
型號: DS33ZH11+
廠商: Maxim Integrated Products
文件頁數(shù): 127/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: 串行
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33Z11 Ethernet Mapper
58 of 172
Figure 8-13 X.86 Encapsulation of the MAC field
Flag(0x7E)
Address(0x04)
Control(0x03)
1st Octect of SAPI(0xfe)
2nd Octect of SAPI(0x01)
Destination Adrs(DA)
Source Adrs(SA)
Length/Type
Number of Bytes
1
6
2
MAC Client Data
46-1500
PAD
FCS for MAC
4
FCS for LAPS
Flag(0x7E)
4
MSB
LSB
The DS33Z11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured
for X.86 mode in the register LI.TX86E. The DS33Z11 provides the following functions:
Control Registers for Address, SAPI, Destination Address, Source Address
32 bit FCS enabled
Programmable X
43+1 scrambling
The sequence of processing performed by the receiver is as follows:
Programmable octets X
43+1 descrambling
Detect the Start Flag (7E)
Remove Rate adaptation octets 7D, DD.
Perform transparency-processing 7D, 5E is converted to 7E and 7D, 5D is converted to 7D.
Check for a valid Address, Control and SAPI fields (LI.TRX86A to LI.TRX86SAPIL)
Perform FCS checking
Detect the closing flag.
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