參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 52/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
145 of 172
RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The
data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss.
Figure 10-9 RMII Receive Interface Functional Timing
RXD[1:0]
CRS_DV
REF_CLK
P
R
E
A
M
B
L
E
F
C
S
10.3 SPI Interface Mode and EEPROM Program Sequence
The DS33Z11 will act as an SPI Master when configured with MODEC[1:0] to read the configuration from an
external Serial EEPROM, such as the Atmel AT25160A. The EEPROM must be programmed with the data
structure shown in Table 10-1. The MOSI (Master Out Slave In) signal can be selectively output on the rising or
falling edge of SPICK. The MISO data can be sampled on rising or falling edge of SPICK based on the CKPHA
pin input. The SPICK is generated by the DS33Z11 at a frequency of 8.33 MHz, derived from an external
SYSCLKI of 100 MHz. The initialization sequence is commenced immediately after power up reset or a rising
edge of the
RST input pin. The SPI master initiates a read with the instruction code 0000x011b; followed by the
address location. The
SPI_CS is held low until the data addressed is read and latched. The DS33Z11 begins
reading the EEPROM at address 0000h. Data is sequentially latched until the last data byte is read and latched.
The indirect MAC registers require a special program sequence at the end of the EEPROM file. Four MAC
registers can be programmed in the EEPROM Mode: SU.MACCR, SU.MACMIIA, SU.MACMIID, and
SU.MACFCR. All other indirect MAC registers do not need to be initialized for EEPROM mode operation. The
indirect MAC registers are programmed using four separate seven-byte records from the EEPROM. An example
is shown in Table 10-2.
Figure 10-10 SPI Master Functional Timing
MOSI
SPICK
CKPHA=0
0
X
0
1
0
7
6
5
4
3
2
1
0
SPI_CS*
0
MISO
012345
6789
10
11
20
21
22
23
24
25
26
27
28
29
30
31
SPICK
CKPHA=1
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