參數資料
型號: DS33ZH11+
廠商: Maxim Integrated Products
文件頁數: 145/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 100CSBGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應用: 數據傳輸
接口: 串行
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 100-LFBGA,CSPBGA
供應商設備封裝: 100-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33Z11 Ethernet Mapper
74 of 172
9.2 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, MCLK configuration, and BPCLK configuration. These registers are preserved to provide
code compatibility with the multiport devices in this product family. The global registers bit descriptions are
presented below.
Register Name:
GL.IDRL
Register Description:
Global ID Low Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Default
0
1
0
Bit 7: ID07 Reserved for future use
Bit 6: ID06 Reserved for future use
Bit 5: ID05 If this bit is set the device contains a RMII interface
Bit 4: ID04 If this bit is set the device contains a MII interface
Bit 3: ID03 If this bit is set the device contains an Ethernet PHY
Bits 0-2: ID00-ID02 A three-bit count that is equal to 000b for the first die revision, and is incremented with each
successive die revision. May not match the two-letter die revision code on the top brand of the device.
Register Name:
GL.IDRH
Register Description:
Global ID High Register
Register Address:
01h
Bit #
7
6
5
4
3
2
1
0
Name
ID15
ID14
ID13
ID12
ID11
ID10
ID09
ID08
Default
0
1
0
Bits 5-7: ID13-15 Number of ports in the device minus 1. (i.e. 000 = 1 port)
Bit 4: ID12 If this bit is set the device has LIU functionality
Bit 3: ID11 If this bit is set the device has a framer
Bit 2: ID10 Reserved for future use
Bit 1: ID09 If this bit is set the device has HDLC or X.86 encapsulation
Bit 0: ID08 If this bit is set the device has inverse multiplexing functionality
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