參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 159/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
87 of 172
Register Name:
TEICR
Register Description:
Transmit Error Insertion Control Register
Register Address:
88h
Bit #
7
6
5
4
3
2
1
0
Name
-
TIER2
TIER1
TIER0
BEI
TSEI
-
Default
0
Bits 3 – 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0]
value of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10
th bit being inverted. A
TEIR[2:0] value of 2 results in every 100
th bit being inverted. Error insertion starts when this register is written to
with a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process,
the new error rate is started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI) When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) This bit causes a bit error to be inserted in the transmit data stream if
and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second
bit error to be inserted, this bit must be set to 0, and back to 1. Note: If this bit transitions more than once between
error insertion opportunities, only one error is inserted.
All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation.
Register Name:
BSR
Register Description:
BERT Status Register
Register Address:
8Ch
Bit #
7
6
5
4
3
2
1
0
Name
-
PMS
-
BEC
OOS
Default
0
Bit 3: Performance Monitoring Update Status (PMS) This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
is asynchronously forced low when the PMU bit goes low. TCLKI and RCLKI must be present.
Bit 1: Bit Error Count (BEC) When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS) When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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