參數(shù)資料
型號(hào): FUSION878A
廠商: CONEXANT SYSTEMS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: PLASTIC, QFP-128
文件頁(yè)數(shù): 11/180頁(yè)
文件大?。?/td> 2067K
代理商: FUSION878A
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3.0 Electrical Interfaces
Fusion 878A
3.5 I2C Serial EEPROM Interface
PCI Video Decoder
3-24
Conexant
100600B
3.5.2 Subsystem Vendor ID
PCI Configuration Header Location 0x2C specifies the subsystem vendor ID and
the subsystem ID. If an external EEPROM is present, the subsystem vendor ID
and subsystem ID and vital product data are uploaded. If an external EEPROM is
not present, the 32 bits of the header register default to 0x0000, and the register
can be programmed using BIOS.
This chapter defines the subsystem vendor ID configuration with and without
an EEPROM present. For more details on the Function 1 definition, refer to
Section 6.1. The Function 0 subsystem vendor ID registers are defined starting on
0x00—Vendor and Device ID Register, and the Function 1 subsystem vendor ID
registers are defined starting on 0x00—Vendor and Device ID Register.
3.5.2.1 EEPROM Upload
at PCI Reset
The 32-bit subsystem IDs are read from the EEPROM by taking control of the
I2C circuit just after PCI reset and performing a 4-byte sequential read access
transaction in the 100 kHz mode, starting at physical address 0xFC. The full read
sequence is detailed in Table 3-7.
If at any time the slave device issues a NACK (because the device is not
present), the sequence is aborted, and the subsystem vendor IDs read
0x00000000. Normally it will take ~660 s to read this DWORD into the PCI
configuration register. If this register is accessed before it is updated, the PCI
target will issue a RETRY.
3.5.2.2 Register Load
from BIOS
The Subsystem IDs register is read-only. However, by enabling SVIDS_EN in the
user-defined PCI configuration control register, the Subsystem Vendor IDs can be
written. Then SVIDS_EN should be disabled. This value needs to be programmed
before OS boots and has access during configuration. This must occur via support
from the BIOS versus the IC driver. If this feature can be supported by software
(and Vital Product Data is not supported), then the external EEPROM is not
required.
Table 3-7. EEPROM Upload Sequence
Master
Slave
Master
Comment
Control
Data
Control
START
0xA0
ACK
Write control byte with slave chip address
0xFC
ACK
Data bytes base address
START
0xA1
ACK
Read control byte with slave chip address
——
0x
ACK
Subsystem ID [15:8] at 0xFC
——
0x
ACK
Subsystem ID [7:0] at 0xFD
——
0x
ACK
Subsystem Vendor ID [15:8] at 0xFE
——
0x
NACK,STOP
Subsystem Vendor ID [7:0] at 0xFF
相關(guān)PDF資料
PDF描述
FVXO-HC53BR-FREQ VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT
FVXO-HC72BR-FREQ VCXO, CLOCK, 0.75 MHz - 180 MHz, HCMOS OUTPUT
FVXO-HC73B-FREQ VCXO, CLOCK, 0.75 MHz - 250 MHz, HCMOS OUTPUT
FVXO-LC52BR-FREQ VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT
FVXO-LC72BR-FREQ VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT
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