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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 8/180頁(yè) |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
3.0 Electrical Interfaces
PCI Video Decoder
3.4 I2C Interface
100600B
Conexant
3-21
3.4 I2C Interface
The I2C bus is a two-wire serial interface. Serial clock and data lines, SCL, and
SDA transfer data between the bus master and the slave device. The I2C bus
within the Fusion 878A supports repeated starts, up to 396.8 kHz timing, and
multi-byte sequential transactions. The I2CRATE signal specifies either 99.2 kHz
or 396.8 kHz timing rate.
If the PCI clock runs at less than the maximum rate,
these rates will slow down proportionately. For details on the I2C register, see
The relationship between SCL and SDA is decoded to provide both a start and
stop condition on the bus. To initiate a transfer on the I2C bus, the master must
transmit a start pulse to the slave device. This is accomplished by taking the SDA
line low while the SCL line is held high. The master should generate a start pulse
only at the beginning of the cycle, or after the transfer of a data byte to or from the
slave. To terminate a transfer, the master must take the SDA line high while the
SCL line is held high. The master may issue a stop pulse at any time during an
I2C cycle. Since the I2C bus interprets any transition on the SDA line during the
high phase of the SCL line as a start or stop pulse, care must be taken to ensure
that data is stable during the high phase of the clock. This is illustrated in
An I2C write transaction consists of sending a START signal, 2 or 3 bytes of
data (checking for a receiver acknowledge after each byte), and a STOP signal.
The write data is supplied from a 24-bit register with bytes I2CDB0, I2CDB1,
and I2CDB2. This 24-bit register is shifted left to provide data serially, with the
MSB as the first bit. An I2C write occurs when the R/W bit in the I2CDB0[0] is
set to a logical low. The system driver can write 2 or 3 bytes of data by selecting
the appropriate value for I2CW3BRA bit.
An I2C read transaction consists of sending a START signal, 1 byte of data
(checking for a receiver acknowledge), reading 1 data byte from the slave,
sending the master NACK, and sending the STOP signal. The data read is shifted
into the I2CDB2 register. An I2C read occurs when the R/W bit in the I2CDB0[0]
is set to a logical 1, illustrated in Figure 3-15.
When the read or write operation is completed, the Fusion 878A sends an
interrupt over the PCI bus to the host controller. The status bit RACK will
indicate if the operation completed successfully with the correct number of slave
acknowledges.
Figure 3-14. The Relationship Between SCL and SDA
Start
Stop
SDA
SCL
879A_045
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