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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 125/180頁(yè) |
| 文件大小： | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.9 VBI Data Output Interface
100600B
Conexant
2-25
The Fusion 878A is able to capture VBI data and store it in the host memory
for later processing by the Fusion 878A VBI decoder software. Two modes of
VBI capture exist: VBI line output mode and VBI frame output mode. Both types
of data may be captured during the same field.
2.9.1 VBI Line Output Mode
In the VBI line output mode, VBI capture occurs during the vertical blanking
interval. The start of VBI data capture is set by the VBI_HDELAY bit in the VBI
Packet Size/Delay register, and is in reference to the trailing edge of the HRESET
signal. The number of DWORDs of VBI data is selected by the user. Each
DWORD contains 4 VBI bytes, and each VBI pixel consists of two VBI samples.
For example, for a given 800 pixel line in the VBI region, there exist 1600 VBI
samples, which are equivalent to 400 DWORDs of VBI data. The VBI_PKT_HI
and VBI_PKT_LO register bits are concatenated to create the 9-bit value for the
number of DWORDs to be captured.
VBI line data capture occurs when the CAPTURE_VBI_EVEN register bit is
enabled for the even field, and CAPTURE_VBI_ODD register bit is enabled for
the odd field. The VBI data is sampled at a rate of 8 × Fsc and is stored in the
FIFO as a sequence of 8-bit samples. Line mode VBI data starts horizontally
beginning at VBI_HDELAY pixels from the trailing edge of HRESET and ending
after the VBI_PKT number of DWORDs. Line mode VBI data starts vertically
beginning at the first line following VRESET and ending at VACTIVE. VBI
register settings can be changed only on a per-frame basis. The VBI timing is
illustrated in Figure 2-17.
Once the VBI data has been captured and stored in the Fusion 878A FIFO, it is
treated as any other type of data. It is output over the PCI bus via RISC
instructions. If the number of VBI lines desired by the user is smaller than the
entire vertical blanking region, the extra data will be discarded by the use of the
SKIP RISC instruction. Alternatively, if the user desires a larger VBI region in the
VBI line output mode, the vertical blanking region can be extended by setting the
VDELAY register to the appropriate value. The VBI line output mode can in
effect extend the VBI region to the entire field. Figure 2-18 illustrates a block
diagram of the VBI section.
Figure 2-17. VBI Timing
VBI Line Data Capture
VBI_PKT #
VBI_HDELAY
VACTIVE
VRESET
HRESET
VDELAY
879A_022
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| FVXO-LC52BR-FREQ | VCXO, CLOCK, 0.75 MHz - 1000 MHz, LVDS OUTPUT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| FUSZ03 | 制造商:Honeywell Sensing and Control 功能描述: |
| FUTURE 1AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2AA PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 2C PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
| FUTURE 3D PLUS | 制造商:Ansmann 功能描述: 制造商:ANSMANN AG 功能描述: |
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