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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類(lèi)： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 150/180頁(yè) |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.13 Byte Alignment
100600B
Conexant
2-47
2.13 Byte Alignment
The video function DMA controllers and PCI initiators are enhanced for byte
resolution on target addresses in packed color modes. The FIFO DWORD-aligned
data is realigned with the correct byte lanes according to the target address.
Byte alignment in the Fusion 878A, which applies only to packed modes,
disables the PCI byte and enables C/BE# during the initial part of a line transfer.
Since the disabled bytes are transferred but not written, they must still be included
in the total byte count. For example, if a non-DWORD aligned target address
begins the line with an offset of 3, then the first byte (byte 0) from the FIFO is
shifted to byte lane 3 and transferred in the first PCI DWORD data with byte
lanes 0–2 disabled. The remaining FIFO bytes (bytes 1–3) are combined with the
following FIFO byte (byte 4) to form the next DWORD transfer. Again, since the
RISC instruction’s byte count represents the number of bytes transferred, not the
number written, the byte count must be increased by 3 in order to account for the
3 disabled bytes that were transferred in the first DWORD.
The target address used is a byte lane offset (relative address), as opposed to
an absolute byte address. So if multiple WRITE instructions are used per video
line, each would have the same byte offset no matter which byte lane SKIP starts
or stops at. Formerly reserved bits [13:12] of the SKIP instruction must contain
the byte offset (two LSB’s of the target address) if they are using byte aligned
addresses.
Byte alignment applies only to video packed mode, and only one byte
alignment may occur per line. A video line may not be transferred to two
segments with byte alignments.
One notable case arises when combining a SKIP and a WRITE with a byte
alignment offset. This may produce a PCI bus WRITE transaction with no byte
enables active. For example, if the first two bytes are skipped combined with a
WRITE and an address offset of 3, the first PCI data phase will have no byte
enables active. The bus master will not prevent the null data transaction because
the DMA will not advance the address. The reason for this is the SKIP consumes
only two bytes, and the address gets advanced only if the entire DWORD is
consumed by going to the bus. The second data phase then consists of 3 bytes
with byte lane 0 disabled.
Table 2-11. Write 640 Pixels in RGB8 Mode
RISC Instruction
Byte Count
Target Address
Pixel/Byte Offset
WRITE
640
F0040004
0
WRITE
641
F0040005
1
WRITE
642
F0040006
2
WRITE
643
F0040007
3
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