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參數(shù)資料
| 型號(hào)： | FUSION878A |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁(yè)數(shù)： | 135/180頁(yè) |
| 文件大?。?/td> | 2067K |
| 代理商： | FUSION878A |
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2.0 Functional Description
Fusion 878A
2.11 Video and Control Data FIFO
PCI Video Decoder
2-34
Conexant
100600B
Planar mode and packed mode data can be present in the FIFOs at the same
time if a bus access latency persists across a FIELD transition, or if packed VBI
data proceeds planar YCrCb data.
2.11.3 Physical Implementation
The three FIFO outputs are delivered in parallel so that the DMA controller can
monitor the FIFOs and perform skipping (reading and discarding data), if
necessary, on all three simultaneously.
Due to the latency in determining the number of DWORDs placed in each
FIFO, a FIFO Full (FFULL) condition is indicated prior to the FIFO count
reaching the maximum FIFO Size. The FIFO is considered FFULL when the
FIFO Count (FCNT) value equals or exceeds the FFULL value. Table 2-8
indicates the FIFO size and FIFO Full/Almost Full counts in units of DWORDs.
A read must occur on the same cycle as FFULL, otherwise data will overflow
and will be overwritten. The maximum bus latencies for various video formats
and modes are shown in Table 2-9.
In planar mode the three FIFOs operate concurrently and independently. In
packed mode, however, the three FIFOs operate in a merged mode to provide the
maximum size buffer. FSIZE1, 2, and 3 indicate the physical size of each FIFO.
FSIZET represents the total buffer size when the FIFOs work together in packed
mode.
2.11.4 FIFO Input/Output Rates
The input and output ports of the Fusion 878A’s FIFO can operate simultaneously
and are asynchronous to one another.
The maximum FIFO input rate is for consecutive writes of PAL video at 17.73
MHz. However, there are never consecutive-pixel-cycle writes to the same FIFO.
The fastest FIFO write sequence is F1, F2, F1, F3. Therefore, the fastest write
rate to any FIFO is less than or equal to half of the pixel rate.
The maximum FIFO output read rate is one FIFO word at the PCI clock rate
(33 MHz). All three FIFOs can be read simultaneously. Some bus systems may be
designed with PCI clocks slower than 33 MHz. The Fusion 878A data FIFO only
supports systems where the maximum input data rate is less than the output data
rate. It can support a input video clock (17.73 MHz) faster than the PCI clock
(16 MHz) as long as the video data rate does not exceed the available PCI burst
rate.
Table 2-8. FIFO Full/Almost Full Counts
FIFO
Size
FFULL
FAFULL
FIFO1
70
68
64
FIFO2
35
34
32
FIFO3
35
34
32
Total
140
136
128
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相關(guān)代理商/技術(shù)參數(shù) |
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| FUSZ03 | 制造商:Honeywell Sensing and Control 功能描述: |
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