Intel
82801E C-ICH
Advance Information Datasheet
11
2.0
Package Information
2.1
Ball Location
This section describes the 82801E C-ICH ball assignment. Figure 3 provides a 421-ball location
diagram. The diagram also indicates general signal groupings. Table 4 lists the 82801E C-ICH
signal assignments by ball number. Table 5 lists the assignments alphabetically by signal name.
Figure 3. Ball Diagram (Top View)
A8684-02
IDE
SMLINK
POWER
MANAGEMENT
SIU
LPC
12
PCI
6
L
P
S
U
H
P
I
A
C
B
E
D
G
F
J
H
L
K
N
M
R
P
U
T
W
V
AA
Y
AC
AB
A
C
B
E
D
G
F
J
H
L
K
N
M
R
P
U
T
W
V
AA
Y
AC
AB
23
22
21
20
19
18
17
16
15
14
13
11
10
9
8
7
5
4
3
2
1
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PIRQ[A]# VSS
NC[4]
GNT[3]#
VSS
AD[28]
VSS
SIU0_
RI#
UART_
CLK
VSS
SIU_
LAD[1]
LAN1_
TXD[1]
VSS
SIU1_
DSR#
SIU1_
RTS#
SIU_
SERIRQ
TP[0]
VSS
THRM#
GPIO[21]
VSS
GNT[0]#
PIRQ[H]#/
GPIO[5]
REQ[0]# NC[5]
AD[26]
AD[22]
FRAME# AD[16]
LAN1_
LCLK
DTR#
VCC3_3
LFSIU_
Vcc1_8
SIU0_
RXD
SIU1_
Vcc1_8
LAD[0]/
LAD[3]/
LDRQ[0]#
GNT[A]#/
GPIO[16]
GNT[5]#/
GPIO[17]
VCC1_8
PIRQ[D]#
AD[30]
VSS
VSS
PAR
AD[13]
AD[20]
EE0_
SHCLK
LAN1_
RXD[0]
VSS
SIU1_
TXD
SIU_
LDRQ#
LAN1_
RSTSYNC
LAN1_
TXD[0]
Vcc3_3
SIU1_
DCD#
SIU_
LAD[2]
VSS LFRAME#/
FWH[4]
LDRQ[1]#
GPIO[1]
REQ[A]#/
GPIO[0]
PIRQ[E]#
PIRQ[C]#
AD[18]
AD[24]
STOP#
AD[15]
VSS
AD[4]
LAN0_
RSTSYNC
EE1_
DOUT
SIU0_
TXD
SIU0_
CTS#
SIU1_
RI#
VSS
LAN1_
TXD[2]
SIU0_
DSR#
SIU1_
CTS#
SIU_
LAD[0]
LAD[1]/
FWH[1]
SIU_
RESET#
V5REF
GNT[1]#
VSS
PIRQ[B]#
REQ[1]#
VSS
Vcc3_3
TRDY#
AD[9]
AD[0]
Vcc1_8
LAN0_
TXD[2]
EE0_
DIN
VSS
SIU0_
RXD
VSS
LAN0_
RXD[2]
EE1_
SHCLK
Vcc3_3
SIU0_
RTS#
SIU_
LAD[3]
LAD[2]/
FWH[2]
SIU_
LCLK
PIRQ[G]#/
GPIO[4]
PIRQ[F]#
REQ[2]#
GNT[2]#
VSS
V5REF Vcc3_3
NC[6]
Vcc3_3
NC[10]
USBP1N
IGNNE#
V_CPU_IO
SDDACK#
Vcc3_3
Vcc3_3
CPUPWRGD
SIORDY
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
VSS
VSS
OC[1]#
NC[7]
USBP1P
NC[9]
RCIN#
VRMPWRGD
SDIOW#
SDD[14]
PDA[1]
V_CPU_IO
SDA[2]
SDIOR#
SDD[5]
PDD[1]
CLK14
PDD[5]
PDCS1#
Vcc3_3
PWROK
VccRTC
NC[1]
SMLINK[0] VSS
RESERVED2
V5REF
VSS
NC[8]
A20GATE
SDCS3#
SDD[0]
SDD[10]
SDD[6]
GPIO[18]
SDD[15]
SDD[12]
PDA[0]
PDD[12]
PDD[6]
PDD[10]
PDIOW#
APICD[1]
NC[2]
RSMRST#
RTCX1
TP[1]
RTCRST#
SMLINK[1]
VSS
OC0#
VSS
GPIO[19]
SDA[1]
SDD[3]
SDD[8]
PDDACK#
VSS
VSS
SDD[4]
VSS
PDD[3]
PDD[7]
VSS
PDD[0]
SERIRQ
FERR#
VccRTC
RTCX2
INTRUDER#
VBIAS
GPIO[24]
Vcc3_3
V5REF
TP[3]
SDA[0]
Vcc3_3
SDD[11]
PDIOR#
PDD[15]
IRQ[15]
SDD[13]
SDD[9]
IRQ[14]
PDD[13]
PDD[8]
PDD[4]
PDD[14]
SPKR
APICD[0]
CLK48
VSS
VSS
VSS
VSS
VSS
VSS
TP[2]
VSS
SDD[1]
PDCS3#
PIORDY
PDDREQ
SDDREQ
SDD[2]
SDD[7]
PDA[2]
VSS
PDD[9]PDD[11]
PDD[2]
V5REF
APICCLK
VSS
NC[3]
Vcc3_3
C/BE[2]#
VSS
VSS
Vcc1_8
PLOCK# Vcc3_3
Vcc3_3
IRDY#
AD[17]
AD[19]
AD[23]
VSS
VSS
HLCOMP
HL[11]
HUBREF
Vcc1_8
Vcc1_8
Vcc1_8
Vcc1_8
VSS
VSS
VSS
Vcc1_8
AD[21]
C/BE[3]#
VSS
AD[27]
AD[25]
HL[2]
HL[1]
HL[0]
VSS
VSS
Vcc1_8
VSS
VSS
VSS
VSS
Vcc1_8
GPIO[28]
GPIO[27]
VSS
GPIO[7]
HL_STB#
HL[10]
HL[4]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RESERVED1
GPIO[13]
GPIO[8]
GPIO[12]
VSS
VSS
HL[7]
HL[8]
HL[5]
Vcc1_8
Vcc1_8
VSS
Vcc1_8
Vcc3_3
Vcc1_8
RI#
SMBDATA
Vcc3_3
PCIRST#GPIO[25]
HL[6]
VSS
CPUSLP#
VSS
VSS
Vcc3_3
Vcc1_8
USBP0N
NC[12]
RSM_PWROK
SMBCLK
VSS
A20M#
SMI#
GPIO[20]
STPCLK#
GPIO[23]
Vcc3_3
Vcc3_3
VSS
USBP0P
SUSCLK
SMBALERT#/
GPIO[11]
NC[11]
INTR
INIT#
SDCS1#
NMI
GPIO[22]
VSS
PCICLK
REQ[3]#
GPIO[6]
AD[29]
AD[31]
VSS
VSS
HL[9]
HL_STB
HL[3]
Vcc1_8
VSS
VSS
Vcc1_8
AD[11] Vcc3_3
C/BE[0]#
AD[6]
AD[7]
AD[10]
Vcc1_8
Vcc1_8
EE1_CS
Vcc3_3
Vcc3_3
LAN0_CLK
EE0_CS
Vcc3_3
AD[2]
Vcc3_3
AD[3]
VSS
SERR#
AD[12]
LAN0_
RXD[1]
LAN0_
TXD[1]
EE1_
DIN
VSS
EE0_
DOUT
Vcc3_3
AD[5]
Vcc3_3
AD[1]
AD[8]
C/BE[1]# AD[14]
VSS
LAN0_
TXD[0]
LAN1_
RXD[1]
Vcc1_8
LAN0_
RXD[0]
Vcc3_3
VSS
PERR#
DEVSEL#
VSS
(CLK66
VSS
VSS
Vcc3_3
Vcc1_8
Vcc1_8
Vcc1_8
Vcc1_8
Vcc3_3