參數(shù)資料
型號： FW82801E
廠商： Intel Corp.
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： 英特爾82801E通訊I / O控制器集線器（丙，出血）
文件頁數(shù)： 26/84頁
文件大小： 1196K
代理商： FW82801E
Intel
82801E C-ICH
26
Advance Information Datasheet
C/BE[3:0]#
I/O
Bus Command and Byte Enables:
The command and byte enable signals
are multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# define the Byte Enables.
C/BE[3:0]#
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0110
Memory Read
0111
Memory Write
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
DAC Mode Address to be latched (target only)
1110
Memory Read Line
1111
Memory Write and Invalidate
All command encodings not shown are reserved. The 82801E C-ICH does
not decode reserved values, and therefore will not respond when a PCI
master generates a cycle using one of the reserved values.
As a target, the 82801E C-ICH can support DAC mode addressing for 44 bits.
CLK14
I
Oscillator Clock:
CLK14 is used for 8254 timers and runs at 14.31818 MHz.
CLK48
I
48 MHz Clock:
CLK48 is used to for the USB controller and runs at 48 MHz.
CLK66
(HLCLK)
I
66 MHz Clock (HLCLK):
CLK66 is used for the hub interface and runs at
66 MHz.
CPUPWRGD
OD
Processor Power Good:
This signal should be connected to the processor’s
PWRGOOD input. This is an open-drain output signal (external pull-up
resistor required) that represents a logical AND of the 82801E C-ICH’s
PWROK and VRMPWRGD signals.
CPUSLP#
O
Processor Sleep:
This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that time,
no snoops occur.
NOTE:
The 82801E C-ICH does not support Sleep states. This signal must
be pulled up through an 8.2 K
resistor to 3.3 V.
DEVSEL#
I/O
Device Select:
The 82801E C-ICH asserts DEVSEL# to claim a PCI
transaction. As an output, the 82801E C-ICH asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal 82801E C-ICH address
or an address destined for the hub interface (main memory or AGP). As an
input, DEVSEL# indicates the response to an 82801E C-ICH-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PCIRST#. DEVSEL# remains tri-stated by the 82801E C-ICH until driven by a
target device.
EE0_CS
EE1_CS
O
EEPROM Chip Select:
These signals are chip-select signals to the
EEPROMs.
EE0_DIN
EE1_DIN
I
EEPROM Data In:
These signals transfer data from the EEPROMs to the
82801E C-ICH. These signals have an integrated pull-up resistor.
EE0_DOUT
EE1_DOUT
O
EEPROM Data Out:
These signals transfer data from the 82801E C-ICH to
the EEPROMs.
EE0_SHCLK
EE1_SHCLK
O
EEPROM Shift Clock:
These signals are the serial shift clock output to the
EEPROMs.
Table 6. 82801E C-ICH Signal Description (Sheet 2 of 11)
Signal
Type
Description
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