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參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 37/84頁 |
| 文件大小： | 1196K |
| 代理商： | FW82801E |
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Intel
82801E C-ICH
Advance Information Datasheet
37
3.2.4
Firmware Hub Interface
3.2.5
PCI Interface
Table 10. Firmware Hub Interface Signals
Name
Type
Description
FWH[3:0]
/LAD[3:0]
I/O
Firmware Hub Signals:
These signals are muxed with LPC address signals.
FWH[4]
/LFRAME#
I/O
Firmware Hub Signals:
This signal is muxed with the LPC LFRAME# signal.
Table 11. PCI Interface Signals (Sheet 1 of 3)
Name
Type
Description
AD[31:0]
I/O
PCI Address/Data:
AD[31:0] is a multiplexed address and data bus. During the first
clock of a transaction, AD[31:0] contain a physical address (32 bits). During
subsequent clocks, AD[31:0] contain data. The 82801E C-ICH drives all 0s on
AD[31:0] during the address phase of all PCI Special Cycles.
C/BE[3:0]#
I/O
Bus Command and Byte Enables:
The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the
Byte Enables.
C/BE[3:0]#
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0110
Memory Read
0111
Memory Write
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
DAC Mode Address to be latched (target only)
1110
Memory Read Line
1111
Memory Write and Invalidate
All command encodings not shown are reserved. The 82801E C-ICH does not
decode reserved values, and therefore will not respond if a PCI master generates a
cycle using one of the reserved values.
As a target, the 82801E C-ICH can support DAC mode addressing for 44 bits.
DEVSEL#
I/O
Device Select:
The 82801E C-ICH asserts DEVSEL# to claim a PCI transaction.
As an output, the 82801E C-ICH asserts DEVSEL# when a PCI master peripheral
attempts an access to an internal 82801E C-ICH address or an address destined
for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the
response to an 82801E C-ICH-initiated transaction on the PCI bus. DEVSEL# is
tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the
82801E C-ICH until driven by a target device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
| FW82801EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FW82801EB S L6TN | 制造商:Intel 功能描述:CONTROLLER: IO CONTROLLER |
| FW82801EB S L73Z | 制造商:Intel 功能描述:I/O Controller Phase Controller 460-Pin BGA |
| FW82801ER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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