參數(shù)資料
型號(hào)： FW82801E
廠商： Intel Corp.
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： 英特爾82801E通訊I / O控制器集線器（丙，出血）
文件頁(yè)數(shù)： 63/84頁(yè)
文件大?。?/td> 1196K
代理商： FW82801E
Intel
82801E C-ICH
Advance Information Datasheet
63
t22
High time
12
36
ns
9
t23
Low time
12
36
ns
9
t24
Rise time
1.0
5.0
ns
9
t25
Fall time
1.0
5.0
ns
9
Hub Interface Clock
fhl
t31
Operating Frequency
66
High time
6.0
ns
9
t32
Low time
6.0
ns
9
t33
Rise time
0.25
1.2
ns
9
t34
Fall time
0.25
1.2
ns
9
t35
CLK66 leads PCICLK
1.0
4.5
3
Table 43. Clock Timings - UART_CLK
Sym
Parameter
Min
Max
Units
Notes
Fig
t1a
Operating Frequency
14.7456
48
MHz
t9a
Frequency Tolerance
2500
PPM
t10a
High Time
7
ns
9
t11a
Low time
7
ns
9
t12a
Rise Time
3
ns
9
t155a
Fall Time
3
ns
9
Table 44. PCI Interface Timing (Sheet 1 of 2)
Sym
Parameter
Min
Max
Units
Notes
Figure
t40
AD[31:0] Valid Delay
2
11
ns
Min: 0pF
Max: 50pF
10
t41
AD[31:0] Setup Time to PCICLK Rising
7
ns
11
t42
AD[31:0] Hold Time from PCICLK Rising
0
ns
11
t43
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PAR, PERR#, PLOCK#, DEVSEL# Valid Delay
from PCICLK Rising
2
11
ns
Min: 0pF
Max: 50pF
10
t44
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output
Enable Delay from PCICLK Rising
2
ns
14
Table 42. Clock Timings (Sheet 2 of 2)
Sym
Parameter
Min
Max
Unit
Notes
Figure
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this
component.
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
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