參數(shù)資料
型號(hào)： FW82801E
廠商： Intel Corp.
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： 英特爾82801E通訊I / O控制器集線器（丙，出血）
文件頁(yè)數(shù)： 62/84頁(yè)
文件大小： 1196K
代理商： FW82801E
Intel
82801E C-ICH
62
Advance Information Datasheet
4.4
AC Characteristics
Table 42. Clock Timings (Sheet 1 of 2)
Sym
Parameter
Min
Max
Unit
Notes
Figure
PCI Clock (PCICLK)
t1
Period
30
33.3
ns
9
t2
High Time
12
ns
9
t3
Low Time
12
ns
9
t4
Rise Time
3
ns
9
t5
Fall Time
3
ns
9
Oscillator Clock (OSC)
t6
Period
67
70
ns
9
t7
High Time
20
9
t8
Low time
20
ns
9
USB Clock (USBCLK)
fclk48
Operating Frequency
48
MHz
t9
Frequency Tolerance
500
ppm
1
t10
High Time
7
ns
9
t11
Low time
7
ns
9
t12
Rise Time
1.2
ns
9
t13
Fall Time
1.2
ns
9
Suspend Clock (SUSCLK)
fsusclk
t14
Operating Frequency
32
KHz
4
High time
10
μs
4
9
t15
Low Time
10
μs
4
9
SMBus Clock (SMBCLK)
fsmb
t18
Operating Frequency
10
16
KHz
High time
4.0
50
μs
2
24
t19
Low time
4.7
μs
24
t20
Rise time
1000
ns
24
t21
Fall time
300
ns
24
I/O APIC Clock (APICCLK)
fioap
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this
component.
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
Operating Frequency
14.32
33.33
MHz
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