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參數(shù)資料
| 型號(hào)： | FW82801E |
| 廠(chǎng)商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線(xiàn)器（丙，出血） |
| 文件頁(yè)數(shù)： | 68/84頁(yè) |
| 文件大?。?/td> | 1196K |
| 代理商： | FW82801E |
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Intel
82801E C-ICH
68
Advance Information Datasheet
Table 49. IOAPIC Bus Timing
Sym
Parameter
Min
Max
Units
Notes
Fig
t120
APICCD[1:0]# Valid Delay from APICCLK Rising
3.0
12.0
ns
10
t121
APICCD[1:0]# Setup Time to APICCLK Rising
8.5
ns
11
t122
APICCD[1:0]# Hold Time from APICCLK Rising
3.0
ns
11
Table 50. SMBus Timing
Sym
Parameter
Min
Max
Units
Notes
Fig
t130
Bus Tree Time Between Stop and Start Condition
4.7
μs
24
t131
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
4.0
μs
24
t132
Repeated Start Condition Setup Time
4.7
μs
24
t133
Stop Condition Setup Time
4.0
μs
24
t134
Data Hold Time
300
ns
24
t135
Data Setup Time
250
ns
24
t136
Device Time Out
25
35
ms
1
t137
Cumulative Clock Low Extend Time (slave device)
25
ms
2
25
t138
Cumulative Clock Low Extend Time (master device)
10
ms
3
25
NOTES:
1. A device will time out when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Table 51. SIU LPC and Serial IRQ Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t150a
SIU_LAD[3:0]/SIU_SERIRQ Valid Delay from
SIU_LCLK Rising
2
11
ns
10
t151a
SIU_LAD[3:0]/SIU_SERIRQ Output Enable Delay from
SIU_LCLK Rising
2
ns
14
t152a
SIU_LAD[3:0]/SIU_SERIRQ Float Delay from
SIU_LCLK Rising
28
ns
12
t153a
SIU_LAD[3:0]/SIU_SERIRQ Setup Time to SIU_LCLK
Rising
7
ns
11
t154a
SIU_LAD[3:0]/SIU_SERIRQ Hold Time from SIU_LCLK
Rising
0
ns
11
t155a
SIU_LDRQ# Valid Delay from SIU_LCLK Rising
2
11
ns
10
t157a
SIU_LFRAME# Setup Time to SIU_LCLK Rising
7
ns
11
t157b
SIU_LAD[3:0] Hold Time from SIU_LCLK Rising
0
ns
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
| FW82801EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FW82801EB S L6TN | 制造商:Intel 功能描述:CONTROLLER: IO CONTROLLER |
| FW82801EB S L73Z | 制造商:Intel 功能描述:I/O Controller Phase Controller 460-Pin BGA |
| FW82801ER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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