- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375989 > FW82801E (Intel Corp.) Intel 82801E Communications I/O Controller Hub (C-ICH) PDF資料下載
參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 41/84頁 |
| 文件大小： | 1196K |
| 代理商： | FW82801E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
Intel
82801E C-ICH
Advance Information Datasheet
41
3.2.7
LPC Interface
3.2.8
Interrupt Interface
Table 13. LPC Interface Signals
Name
Type
Description
LAD[3:0]
/FWH[3:0]
I/O
LPC Multiplexed Command, Address, Data:
Internal pull-ups are provided.
LFRAME#
/FWH[4]
O
LPC Frame:
LFRAME# indicates the start of an LPC cycle, or an abort.
LDRQ[1:0]#
I
LPC Serial DMA/Master Request Inputs:
These signals are used to request DMA or
bus master access. Typically, they are connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
Table 14. Interrupt Signals
Name
Type
Description
SERIRQ
I/O
Serial Interrupt Request:
This pin implements the serial interrupt protocol.
PIRQ[A:D]#
I/OD
PCI Interrupt Requests:
In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section.
Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts.
PIRQ[E:F]#
PIRQ[G]#/GPIO[4]
PIRQ[H]#/GPIO[5]
I/OD
PCI Interrupt Requests:
In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section.
Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21,
PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If
not needed for interrupts, PIRQ[H:G] can be used as GPIO.
IRQ[14:15]
I
Interrupt Request 14:15:
These interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the primary controller and
IRQ15 is used by the drives connected to the secondary controller.
APICCLK
I
APIC Clock:
The APIC clock runs at 33.333 MHz.
APICD[1:0]
I/OD
APIC Data:
These bidirectional open drain signals are used to send and
receive data over the APIC bus. As inputs, the data is valid on the rising edge
of APICCLK. As outputs, new data is driven from the rising edge of the
APICCLK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FWB150 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB151 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB1510 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB152 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
| FWB154 | 1.5 AMP FAST RECOVERY BRIDGE RECTIFIERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
| FW82801EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| FW82801EB S L6TN | 制造商:Intel 功能描述:CONTROLLER: IO CONTROLLER |
| FW82801EB S L73Z | 制造商:Intel 功能描述:I/O Controller Phase Controller 460-Pin BGA |
| FW82801ER | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。