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參數(shù)資料
| 型號： | FW82801E |
| 廠商： | Intel Corp. |
| 英文描述： | Intel 82801E Communications I/O Controller Hub (C-ICH) |
| 中文描述： | 英特爾82801E通訊I / O控制器集線器（丙，出血） |
| 文件頁數(shù)： | 84/84頁 |
| 文件大?。?/td> | 1196K |
| 代理商： | FW82801E |
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Intel
82801E C-ICH
84
Advance Information Datasheet
5.3.1
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity (e.g.,
opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 62.
In this example, Vector 1 applies all “0s” to the chain inputs. The outputs being non-inverting, will
consistently produce a “1” at the XOR output on a good board. One short to Vcc (or open floating
to Vcc) will result in a “0” at the chain output, signaling a defect.
Likewise, applying Vector 7 (all “1s”) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a “1” at the XOR chain output on a good
board. One short to Vss (or open floating to Vss) will result in a “0” at the chain output, signaling a
defect. It is important to note that the number of inputs pulled to “1” will affect the expected chain
output value. If the number of chain inputs pulled to “1” is even, then expect “1” at the output. If
the number of chain inputs pulled to “1” is odd, expect “0” at the output.
Continuing with the example in Table 62, as the input pins are driven to “1” across the chain in
sequence, the XOR Output will toggle between “0” and “1.” Any break in the toggling sequence
(e.g., “1011”) will identify the location of the short or open.
5.3.1.1
Test Pattern Consideration for XOR Chain 4
When the 82801E C-ICH is operated with the Hub Interface in “Normal” mode (See “Functional
Straps” on page 49), the HL_STB and HL_STB# signals must always be driven to complementary
logic levels. For example, if a “1” is driven on HL_STB, then a “0” must be driven on HL_STB#
and vice versa. This will need to be considered in applying test patterns to this chain.
When the 82801E C-ICH is operated with the Hub Interface in “Enhanced” mode there are no
restrictions on the values that may be driven onto the HL_STB and HL_STB# signals.
Table 62. XOR Test Pattern Example
Vector
Input
Pin 1
Input
Pin 2
Input
Pin 3
Input
Pin 4
Input
Pin 5
Input
Pin 6
XOR
Output
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
3
1
1
0
0
0
0
1
4
1
1
1
0
0
0
0
5
1
1
1
1
0
0
1
6
1
1
1
1
1
0
0
7
1
1
1
1
1
1
1
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| FW82801E S L5AW | 制造商:Intel 功能描述:I/O Controller Phase Controller 421-Pin BGA |
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