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參數(shù)資料
| 型號： | HYB18T256324F-22 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 21/80頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-22 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
21
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
14.During action WRITE/A an ACT or a PRE command
on another bank is allowed any time. A new WR or
WR/A command on another bank has to be
separated by at least one NOP from the ongoing
command. RD is not allowed before t
WTR
is met.
RD/A is not allowed during an ongoing WRITE/A
action.
15.During action READ and READ/A an ACT or a PRE
command on another bank is allowed any time. A
new RD or RD/A command on another bank has to
be separated by at least one NOP from the ongoing
command. A WR or WR/A command on another
bank has to meet t
RTW
.
2.4.3
Function Truth Table for CKE
1. CKE
n
is the logic step at clock edge n; CKE
n-1
was
the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics
RAM immediatly prior to clock edge n.
3. COMMAND is the command registered at clock
edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or
reserved.
5. DESEL or NOP commands should be issued on
any clock edges occuring during the t
XSR
period. A
minimum of 200 clock cycles is required before
applying any other valid command.
Table 8
CKE
n-1
L
Function Truth Table II (CKE Table)
CKE
n
L
Power Down
Self Refresh
H
Power Down
Self Refresh
L
All Banks Idle
Bank(s) Active
All Banks Idle
CURRENT STATE
COMMAND
ACTION
X
X
DESEL or NOP
DESEL or NOP
DESEL or NOP
DESEL or NOP
Auto Refresh
stay in Power Down
stay in Self Refresh
Exit Power Down
Exit Self Refresh
5
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
L
H
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
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| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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