參數(shù)資料
型號(hào)： HYB18T256324F-22
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 30/80頁(yè)
文件大小： 2026K
代理商： HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
30
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.4.5
When the Low Power extended mode register is set, the device enters a low power mode of operation. This mode
is not enabled for the HYB18T256324F–[16/20/22]. Setting this bit to HIGH will have no effect on the behavior of
the GDDR3 DRAM.
Low Power
3.4.6
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set
to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3
DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will
be driven onto the DQ bus after t
RIDon
following the EMRS command that sets A10 to 1. The Vendor Code and
Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After t
RDoff
following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must
be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation.
Vendor Code and Revision Identification
Note:Please refer to Revision Release Note for Revision ID value
Figure 13
Timing of Vendor Code and Revision ID generation on DQ[7:0]
Table 17
Revision Identification
DQ[7:4]
0001
Revision ID and Vendor Code
Infineon Vendor Code
DQ[3:0]
0010
Table 18
Parameter
Vendor Code and Revision ID Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
–1.6
min
EMRS to DQ on time
t
RIDon
EMRS to DQ off time
t
RIDoff
Limit Values
–2.0
min
—
—
Unit
Notes
–2.2
max
20
20
max
20
20
min
—
—
max
20
20
—
—
ns
ns
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