參數(shù)資料
型號(hào)： HYB18T256324F-22
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 35/80頁(yè)
文件大小： 2026K
代理商： HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
35
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.7
Writes (WR)
3.7.1
Write Basic Information
Figure 19
Write Command
Write bursts are initiated with a WR command, as
shown in
Figure 19
. The column and bank addresses
are provided with the WR command, and Auto
Precharge is either enabled or disabled for that access.
The length of the burst initiated with a WR command is
always four. There is no interruption of WR bursts. The
two least significant address bits A0 and A1 are ’Don’t
Care’.
For WR commands with Autoprecharge the row being
accessed is precharged
t
WR/A
after the completion of
the burst. If
t
RAS
(min) is violated the begin of the internal
Autoprecharge will be performed one cycle after
t
RAS
(min) is met.
t
WR/A
can be programmed in the Mode
Register. Choosing high values for
t
WR/A
will prevent the
chip to delay the internal Autoprecharge in order to
meet
t
RAS
(min).
During WR bursts data will be registered with the edges
of WDQS. The write latency can be programmed during
Extended Mode Register Set. The first valid data is
registered with the first valid rising edge of WDQS
following the WR command. The externally provided
WDQS must switch from HIGH to LOW at the beginning
of the preamble. There is also a postamble requirement
before the WDQS returns to HIGH. The WDQS signal
can only transition when data is applied at the chip input
and during pre- and postambles.
t
DQSS
is the time between WR command and first valid
rising edge of WDQS. Nominal case is when WDQS
edges are aligned with edges of external CLK.
Minimum and maximum values of
t
DQSS
define early
and late WDQS operation. Any input data will be
ignored before the first valid rising WDQS transition.
t
DQSL
and
t
DQSH
define the width of low and high phase
of WDQS. The sum of t
DQSL
and
t
DQSH
has to be
t
CK
.
Table 21
Parameter
ACT Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
max
37.2
—
24.0
8 x t
REFI
8.0
—
Unit Notes
–1.6
max
—
8 x t
REFI
—
–2.2
max
—
8 x t
REFI
—
min
37.2
24.0
8.0
min
39.6
26.2
8.8
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command
period
Row to Column Delay Time for
Reads
Row to Column Delay Time for
Writes
t
RC
t
RAS
t
RRD
ns
ns
ns
t
RCDRD
16.0
—
16.0
—
17.5
—
ns
t
RCDWR
t
RCDWR(min)
=
t
RCDRD(min)
- (WL + 1) x t
CK(min)
ns
#,+
#,+
2!3
#+%
#!3
7%
! !
!
"! "!
#!
"!
#! #OLUMN !DDRESS
"! "ANK !DDRESS
$ONgT #ARE
!
!
!
!
!
! 0
!0 !UTO0RECHARGE
#3
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