參數(shù)資料
型號(hào): HYB18T256324F-22
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù): 37/80頁(yè)
文件大?。?/td> 2026K
代理商: HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
37
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
Table 23
Parameter
WR Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
2
Unit
Notes
–1.6
–2.2
min
2
max
max
min
2
max
CAS(a) to CAS(b) Command period
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS latching
transition
Data-in and Data Mask to WDQS Setup
Time
Data-in and Data Mask to WDQS Hold
Time
Data-in and DM input pulse width (each
input)
WDQS input low pulse width
WDQS input high pulse width
WDQS Write Preamble Time
WDQS Write Postamble Time
Write to Read Command Delay
Write Recovery Time
t
CCD
t
CK
1)
1)
t
CCD
is either for gapless consecutive writes or gapless consecutive reads
2) Timing parameters defined with Graphics DRAM terminations on.
3)
t
DQSL
. and
t
DQSH
apply for the Write preamble and postamble as well.
4)
t
DQSS
WL -
0.25
0.35
WL
+0.25
WL -
0.25
0.375 —
WL
+0.25
WL -
0.25
0.375 —
WL
+0.25
t
CK
t
DS
ns
2)
t
DH
0.35
0.375 —
0.375 —
ns
2)
t
DIPW
0.45
0.45
0.45
t
CK
t
DQSL
t
DQSH
t
WPRE
t
WPST
t
WTR
t
WR
0.45
0.45
0.75
0.75
6.0
11.0
1.25
1.25
0.45
0.45
0.75
0.75
6.0
11.0
1.25
1.25
0.45
0.45
0.75
0.75
6.6
11.0
1.25
1.25
t
CK
t
CK
t
CK
t
CK
ns
ns
3)
3)
2)4)
tWTR
and
t
WR
start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQSx
2)4)
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