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參數(shù)資料
| 型號(hào)： | HYB18T256324F-22 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁(yè)數(shù)： | 67/80頁(yè) |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-22 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Data Sheet
67
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
4.3
DC & AC Logic Input Levels.
(0°C
≤
T
C
≤
+85°C,
V
DD
= +2.0 V ± 0.10 V,
V
DDQ
= +2.0 V ± 0.10 V, see
Table 1
)
1. The DC values define where the input slew rate requirements are imposed, and the input signal must not
violate these levels in order to maintain a valid level.
2. Input slew rate = 2 V/ns. If the input slew rate is less than 2 V/ns, input timing may be compromised. All slew
rates are measured between
V
IL(DC)
and
V
IH(DC)
.
3.
V
IH
overshoot :
V
IH(MAX)
=
V
DDQ
+0.5 V for a pulse width
≤
500ps and the pulse width cannot be greater than 1/3
of the cycle rate.
V
IL
undershoot:
V
IL(MIN)
= 0 V for a pulse width
≤
500ps and the pulse width cannot be greater
than 1/3 of the cycle rate.
4.4
Differential Clock DC and AC Levels
(0°C
≤
T
C
≤
+85°C,
V
DD
= +2.0 V ± 0.10 V,
V
DDQ
= +2.0 V ± 0.10 V, see
Table 1
)
1. All voltages referenced to
V
SS
2.
V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK.
3. The value of
V
IX
is expected to equal 0.7 x
V
DDQ
of the transmitting device and must track variations in the DC
level of the same.
Table 34
Parameter
DC & AC Logic Input Levels
Symbol
Limit Values
min.
0.7 *
V
DDQ
+ 0.15
—
0.7 *
V
DDQ
+0.4
—
0.8 *
V
DDQ
-0.3
Unit Notes
max.
—
0.7 *
V
DDQ
-0.15
—
0.7 *
V
DDQ
- 0.4
V
DDQ
+ 0.3
0.2 *
V
DDQ
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logoc low, DC, RESET pin
V
IH(DC)
V
IL(DC)
V
IH (AC)
V
IL(AC)
V
IHR(DC)
V
ILR(DC)
V
V
V
V
V
V
1
1
2,3
2,3
Table 35
Parameter
Differential Clock DC and AC Input conditions
Symbol
Limit Values
min.
V
REF
- 0.1
0.42
0.3
Unit
Note
s
max.
V
REF
+ 0.1
V
DDQ
+ 0.3
V
DDQ
Clock Input Mid-Point Voltage, CLK and CLK
V
MP(DC)
Clock Input Voltage Level, CLK and CLK
Clock DC Input Differential Voltage, CLK and
CLK
Clock AC Input Differential Voltage, CLK and
CLK
AC Differential Crossing Point Input Voltage
V
IX(AC)
V
V
V
1
1
1
V
IN(DC)
V
ID(DC)
V
ID(AC)
0.5
V
DDQ
+ 0.5
V
1, 2
V
REF
- 0.15
V
REF
+ 0.15
V
1, 3
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