- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370782 > HYB18T256324F-22 (INFINEON TECHNOLOGIES AG) 256-Mbit GDDR3 DRAM [600MHz] PDF資料下載
參數(shù)資料
| 型號(hào)： | HYB18T256324F-22 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁(yè)數(shù)： | 34/80頁(yè) |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-22 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
34
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.6
Bank / Row Activation (ACT)
Figure 17
Activating a specific row
Before a READ or WRITE command can be issued to
a bank, a row in that bank must be opened. This is
accomplished via the ACT command, which selects
both the bank and the row to be activated.
After opening a row by issuing an ACT command, a
READ or WRITE command may be issued after t
RCD
to
that row.
A subsequent ACT command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACT commands to the
same bank is defined by t
RC
.
A subsequent ACT command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACT
commands to different banks is defined by t
RRD
.
There is a minimum time t
RAS
between opening and
closing a row.
Figure 18
Bank Activation timing
#,+
#,+
2!3
#+%
#!3
7%
! !
"!
"!
2!
"!
2! 2OW !DDRESS
"! "ANK !DDRESS
$ONgT #ARE
#3
#,+
#,+
T
22$
T
2#$
T
2! 3
T
2#
!#4
!#4
2 7
#OM
02%
!#4
2OW
2OW
#OL
! !
!
2OW
"8
"9
"9
"!
"!
"9
"9
2OW 2OW !DDRESS
#OL
#OLUMN !DDRESS
"8
"ANK 8
"9
"ANK 9
2 7 2%!$ OR 72)4% COMMAND
02% 02%#(!2'% COMMAND
!#4 !#4 )6!4% COMMAND
$ONgT #ARE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256400AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256160A-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AFL-3 | 256 Mbi t DDR2 SDRAM |
| HYB18T256400AFL-37 | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AFL-37 | 256 Mbi t DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。