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| 型號： | ISP1564ET,551 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA100 |
| 封裝： | 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100 |
| 文件頁數(shù)： | 22/99頁 |
| 文件大小： | 493K |
| 代理商： | ISP1564ET,551 |
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ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
28 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
8.2.3.5
PMCSR_BSE register
The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge-specic functionality and is required for all PCI-to-PCI bridges. The bit allocation of
this register is given in Table 38.
8
PMEE
PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is
disabled. This bit defaults to logic 0, if the function does not support the PME# generation from
D3cold. If the function supports PME# from D3cold, then this bit is sticky and must explicitly be
cleared by the operating system each time the operating system is initially loaded.
7 to 2
reserved
-
1 to 0
PS[1:0]
Power State: This two-bit eld is used to determine the current power state of the EHCI function
and to set the function into a new power state. The denition of the eld values is given as:
00b — D0
01b — D1
10b — D2
11b — D3hot
If the software attempts to write an unsupported, optional state to this eld, the write operation
must complete normally on the bus; however, data is discarded and no status change occurs.
Table 37.
PMCSR - Power Management Control/Status register bit description …continued
Address: Value read from address 34h + 4h
Bit
Symbol
Description
Table 38.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation
Address: Value read from address 34h + 6h
Bit
7
6
5
4
3
2
1
0
Symbol
BPCC_EN
B2_B3#
reserved
Reset
00000000
Access
RRRRRRRR
Table 39.
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description
Address: Value read from address 34h + 6h
Bit
Symbol
Description
7
BPCC_EN Bus Power or Clock Control Enable:
1 — Indicates that the bus power or clock control mechanism as dened in Table 40 is enabled.
0 — Indicates that the bus power or control policies as dened in Table 40 are disabled.
When the bus power or clock control mechanism is disabled, the bridge’s PMCSR Power State (PS)
eld cannot be used by the system software to control the power or clock of the bridge’s secondary
bus.
6
B2_B3#
B2 or B3 support for D3hot: The state of this bit determines the action that is to occur as a direct
result of programming the function to D3hot.
1 — Indicates that when the bridge function is programmed to D3hot, its secondary bus’s PCI clock will
be stopped (B2).
0 — Indicates that when the bridge function is programmed to D3hot, its secondary bus will have its
power removed (B3).
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
5 to 0
reserved
-
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| ISP1564ETGA | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564ET-S | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ET-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ETUM | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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