參數(shù)資料
型號(hào)： ISP1564ET,551
廠商： ST-ERICSSON
元件分類(lèi)： 總線(xiàn)控制器
英文描述： PCI BUS CONTROLLER, PBGA100
封裝： 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁(yè)數(shù)： 55/99頁(yè)
文件大?。?/td> 493K
代理商： ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
58 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
The reserved bits must always be written with the reset value.
Table 91.
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit allocation
Address: Content of the base address register + 54h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
PRSC
OCIC
PSSC
PESC
CSC
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
LSDA
PPS
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
PRS
POCI
PSS
PES
CCS
Reset
00000000
Access
R/W
Table 92.
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description
Address: Content of the base address register + 54h
Bit
Symbol
Description
31 to 21
reserved
-
20
PRSC
Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can
write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — Port reset is not complete.
1 — Port reset is complete.
19
OCIC
Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on
a per-port basis. This bit is set when the root hub changes the POCI (Port Overcurrent Indicator) bit.
The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in POCI.
1 — POCI has changed.
18
PSSC
Port Suspend Status Change: This bit is set when the resume sequence is completed. This
sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD
can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when Reset
Status Change is set.
0 — Resume is not completed.
1 — Resume is completed.
17
PESC
Port Enable Status Change: This bit is set when hardware events cause the PES (Port Enable
Status) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in PES.
1 — Change in PES.
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