參數(shù)資料
型號(hào): ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁(yè)數(shù): 37/99頁(yè)
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
41 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
11.1.5 HcInterruptEnable register
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. A hardware interrupt is requested on the host
bus if the following conditions occur:
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to
a bit in this register leaves the corresponding bit unchanged. On a read, the current value
of this register is returned. The bit allocation is given in Table 57.
5
FNO
Frame Number Overow: This bit is set when the Most Signicant Bit (MSB) of HcFmNumber
(bit 15) changes value, or after HccaFrameNumber is updated.
4UE
Unrecoverable Error: This bit is set when the host controller detects a system error not related to
USB. The host controller must not proceed with any processing or signaling before the system error
is corrected. The HCD clears this bit after the host controller is reset.
3RD
Resume Detected: This bit is set when the host controller detects that a device on the USB is
asserting resume signaling. This bit is set by the transition from no resume signaling to resume
signaling. This bit is not set when the HCD sets the USBRESUME state.
2SF
Start-of-Frame: At the start of each frame, this bit is set by the host controller and an SOF token is
generated at the same time.
1
WDH
Write-back Done Head: This bit is immediately set after the host controller has written HcDoneHead
to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD
must only clear this bit after it has saved the content of HccaDoneHead.
0SO
Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the
update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] eld (bits 17 to 16 of
HcCommandStatus).
Table 56.
HcInterruptStatus - Host Controller Interrupt Status register bit description …continued
Address: Content of the base address register + 0Ch
Bit
Symbol
Description
Table 57.
HcInterruptEnable - Host Controller Interrupt Enable register bit allocation
Address: Content of the base address register + 10h
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
OC
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
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