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| 型號： | ISP1564ET,551 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA100 |
| 封裝： | 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100 |
| 文件頁數(shù)： | 61/99頁 |
| 文件大?。?/td> | 493K |
| 代理商： | ISP1564ET,551 |
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ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
63 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
11.2.4 HCSP-PORTROUTE register
The HCSP-PORTROUTE (Companion Port Route Description) register is an optional
read-only eld that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its
address is content of the base address register + 0Ch.
This eld is a 15-element nibble array, each 4 bits is one array element. Each array
location corresponds one-to-one with a physical port provided by the host controller. For
example, PORTROUTE[0] corresponds to the rst PORTSC port, PORTROUTE[1] to the
Table 97.
HCCPARAMS - Host Controller Capability Parameters register bit allocation
Address: Content of the base address register + 08h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
IST[3:0]
reserved
PFLF
64AC
Reset
00010010
Access
RRRRRRRR
Table 98.
HCCPARAMS - Host Controller Capability Parameters register bit description
Address: Content of the base address register + 08h
Bit
Symbol
Description
31 to 8
reserved
-
7 to 4
IST[3:0]
Isochronous Scheduling Threshold: Default = implementation dependent. This eld indicates,
relative to the current position of the executing host controller, where software can reliably update
the isochronous schedule. When IST[3] is logic 0, the value of the least signicant three bits
indicates the number of microframes a host controller can hold a set of isochronous data structures,
one or more, before ushing the state. When IST[3] is logic 1, the host software assumes the host
controller may cache an isochronous data structure for an entire frame.
3 to 2
reserved
-
1
PFLF
Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared, the
system software must use a frame list length of 1024 elements with the host controller. The
USBCMD register FLS[1:0] (bits 3 and 2) is read-only and must be cleared. If PFLF is set, the
system software can specify and use a smaller frame list, and congure the host through the FLS
bit. The frame list must always be aligned on a 4 kB page boundary to ensure that the frame list is
always physically contiguous.
0
64AC
64-bit Addressing Capability: This eld contains the addressing range capability.
0 — Data structures using 32-bit address memory pointers.
1 — Data structures using 64-bit address memory pointers.
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| ISP1564ETGA | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564ET-S | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ET-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ETUM | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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