參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 75/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
76 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
These elds read logic 0, if the PP bit is logic 0.
11.4 Miscellaneous registers
The ISP1564 employs mechanisms to improve throughput in USB transfers. In certain
system in which PCI throughput is low, however, these mechanisms may fail. The system
tuning register provide a mean to disable these mechanisms using software. For bit
allocation of the register, see Table 116.
3
PEDC
Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed.
Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is
disabled because of the appropriate conditions existing at the EOF2 point. For denition of port
error, refer to Chapter 11 of
Universal Serial Bus Specication Rev. 2.0. Software clears this bit
by setting it.[1]
2
PED
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. Default = 0. Ports can
only be enabled by the host controller as a part of the reset and enable sequence. Software
cannot enable a port by writing logic 1 to this eld. The host controller will only set this bit when
the reset sequence determines that the attached device is a high-speed device. Ports can be
disabled by either a fault condition or by host software. The bit status does not change until the
port state has changed. There may be a delay in disabling or enabling a port because of other
host controller and bus events. When the port is disabled, downstream propagation of data is
blocked on this port, except for reset.[1]
1
ECSC
Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change.
Default = 0. This bit indicates a change has occurred in the ECCS of the port. The host
controller sets this bit for all changes to the port device connect status, even if the system
software has not cleared an existing connect status change. For example, the insertion status
changes two times before the system software has cleared the changed condition, hub
hardware will be setting an already-set bit, that is, the bit will remain set. Software clears this bit
by writing logic 1 to it.[1]
0
ECCS
Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no
device is present. Default = 0. This value reects the current state of the port and may not
directly correspond to the event that caused the ECSC bit to be set.[1]
Table 115. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description …continued
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2
Bit
Symbol
Description
Table 116. System Tuning register bit allocation
Address: Content of the base address register + 6Ch
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
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