參數(shù)資料
型號(hào)： ISP1564ET,551
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA100
封裝： 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁(yè)數(shù)： 24/99頁(yè)
文件大?。?/td> 493K
代理商： ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
29 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
8.2.3.6
Data register
The Data register is an optional, 1-byte register that provides a mechanism for the
function to report state dependent operating data, such as power consumed or heat
dissipated. Table 41 shows the bit description of the register.
8.2.4 VPD register
8.2.4.1
VPD_Cap_ID register
The Capability Identier (Cap_ID) register when read by the system software as 03h
indicates that the data structure currently being pointed to is the VPD_Data structure. The
bit description of the register is given in Table 43.
8.2.4.2
VPD_Next_Item_Ptr register
The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in
the function’s capability list. The value given is an offset into the function’s PCI
conguration space. If the function does not implement any other capabilities dened by
the PCI-SIG for inclusion in the capabilities list, or if the power management is the last
item in the list, then this register must be set to 00h. See Table 44.
Table 40.
PCI bus power and clock control
Originating device’s
bridge PM state
Secondary bus
PM state
Resultant actions by bridge (either direct or indirect)
D0
B0
none
D1
B1
none
D2
B2
clock stopped on secondary bus
D3hot
B2, B3
clock stopped and PCI VCC removed from secondary
bus (B3 only); for denition of B2_B3#, see Table 39
D3cold
B3
none
Table 41.
Data register bit description
Address: Value read from address 34h + 7h
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
DATA[7:0]
R
00h*
DATA: This register is used to report the state dependent data requested
by the D_S eld of the PMCSR register. The value of this register is scaled
by the value reported by the DS eld of the PMCSR register.
Table 42.
VPD specic registers
Offset
Register
Value read from address 34h + 8h
Vital Product Data Capability Identier (VPD_Cap_ID)
Value read from address 34h + 9h
Vital Product Data Next Item Pointer (VPD_Next_Item_Ptr)
Value read from address 34h + Ah
Vital Product Data Address (VPD_Addr)
Value read from address 34h + Ch
Vital Product Data Data (VPD_Data)
Table 43.
VPD_Cap_ID - Vital Product Data Capability Identier register bit description
Address: Value read from address 34h + 8h
Legend: * reset value
Bit
Symbol
Access
Value Description
7 to 0
VPD_CAP_ID[7:0]
R
03h*
VPD Capability ID: Capability structure ID; for details, refer to Appendix I of
PCI Local Bus Specication Rev. 2.2
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參數(shù)描述
ISP1564ETGA 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564ET-S 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ET-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ETUM 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564HL 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller
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