參數(shù)資料
型號(hào): ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁(yè)數(shù): 78/99頁(yè)
文件大?。?/td> 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
7 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
C/BE[2]#
35
F5
I/O
byte 2 of multiplexed PCI bus command and byte enable
PCI pad; 3.3 V signaling
FRAME#
36
G5
I/O
PCI cycle frame; driven by the master to indicate the beginning and
duration of an access
PCI pad; 3.3 V signaling
IRDY#
37
H5
I/O
PCI initiator ready; indicates the ability of the initiating agent to complete
the current data phase of a transaction
PCI pad; 3.3 V signaling
TRDY#
38
J5
I/O
PCI target ready; indicates the ability of the target agent to complete the
current data phase of a transaction
PCI pad; 3.3 V signaling
DEVSEL#
39
H6
I/O
PCI device select; indicates if any device is selected on the bus
PCI pad; 3.3 V signaling
VCC(IO)
40
K5
-
I/O pads supply voltage; see Section 7.8
STOP#
41
G6
I/O
PCI stop; indicates that the current target is requesting the master to
stop the current transaction
PCI pad; 3.3 V signaling
CLKRUN#
42
K6
I/O
PCI CLKRUN signal; pull down to ground through a 10 k
resistor
PCI pad; 3.3 V signaling; open-drain
REG(1V8)
43
J6
-
1.8 V regulator output voltage; only for voltage conditioning; cannot be
used to supply power to external components; see Section 7.8
PERR#
44
J7
I/O
PCI parity error; used to report data parity errors during all PCI
transactions, except a special cycle
PCI pad; 3.3 V signaling
SERR#
45
J8
O
PCI system error; used to report address parity errors and data parity
errors on the Special Cycle command, or any other system error in
which the result will be catastrophic
PCI pad; 3.3 V signaling; open-drain
GNDA
46
K7
-
analog ground
PAR
47
K8
I/O
PCI parity
PCI pad; 3.3 V signaling
C/BE[1]#
48
K9
I/O
byte 1 of multiplexed PCI bus command and byte enable
PCI pad; 3.3 V signaling
GND
49
H7
-
ground
AD[15]
50
K10
I/O
bit 15 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
AD[14]
51
J10
I/O
bit 14 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
AD[13]
52
H10
I/O
bit 13 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
AD[12]
53
H9
I/O
bit 12 of multiplexed PCI address and data
PCI pad; 3.3 V signaling
Table 2.
Pin description …continued
Symbol[1]
Pin
Type[2]
Description
LQFP100
TFBGA100
相關(guān)PDF資料
PDF描述
ISP1582BS,557 UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
ISP1583ET1,118 UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
ISP1583BS,551 UNIVERSAL SERIAL BUS CONTROLLER, PQCC64
ISP1583ET2 UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
ISP1761ET,518 UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1564ETGA 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA,便攜式音頻/視頻,智能電話 接口:I²C,2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)(4x4) 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564ET-S 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ET-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ETUM 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA,便攜式音頻/視頻,智能電話 接口:I²C,2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)(4x4) 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564HL 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller