參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 44/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
48 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
11.1.12 HcBulkCurrentED register
This register contains the physical address of the current endpoint of the bulk list. The
endpoints are ordered according to their insertion to the list because the bulk list must be
served in a round-robin fashion.
The bit allocation is given in Table 71.
[1]
The reserved bits must always be written with the reset value.
11.1.13 HcDoneHead register
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA. Table 73 contains the bit allocation
of the register.
Table 71.
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation
Address: Content of the base address register + 2Ch
Bit
31
30
29
28
27
26
25
24
Symbol
BCED[27:20]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
BCED[19:12]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
BCED[11:4]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BCED[3:0]
reserved[1]
Reset
00000000
Access
R/W
Table 72.
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description
Address: Content of the base address register + 2Ch
Bit
Symbol
Description
31 to 4
BCED[27:0]
Bulk Current ED: This is advanced to the next ED after the host controller has served the current
ED. The host controller continues processing the list from where it left off in the last frame. When it
reaches the end of the bulk list, the host controller checks CLF (bit 1 of HcCommandStatus). If the
CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to
HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in
the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value
of this register. This is initially set to logic 0 to indicate the end of the bulk list.
3 to 0
reserved
-
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