參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 70/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
71 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
The reserved bits must always be written with the reset value.
11.3.6 ASYNCLISTADDR register
This 32-bit register contains the address of the next asynchronous queue head to be
executed. If the host controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of
the HCCPARAMS register), the most signicant 32 bits of every control data structure
address comes from the CTRLDSSEGMENT register. For details on the
CTRLDSSEGMENT register, refer to
Enhanced Host Controller Interface Specication for
Universal Serial Bus Rev. 1.0. Bits 4 to 0 of this register always return zeros when read.
The memory structure referenced by the physical memory pointer is assumed as 32 bytes
(cache aligned). For bit allocation, see Table 110.
Table 108. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Content of the base address register + 34h
Bit
31
30
29
28
27
26
25
24
Symbol
BA[19:12]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
BA[11:4]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
BA[3:0]
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
Reset
00000000
Access
R/W
Table 109. PERIODICLISTBASE - Periodic Frame List Base Address register bit description
Address: Content of the base address register + 34h
Bit
Symbol
Description
31 to 12
BA[19:0]
Base Address: These bits correspond to memory address signals 31 to 12, respectively.
11 to 0
reserved
-
Table 110. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation
Address: Content of the base address register + 38h
Bit
31
30
29
28
27
26
25
24
Symbol
LPL[26:19]
Reset
00000000
Access
R/W
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