參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 66/99頁
文件大?。?/td> 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
68 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
11.3.3 USBINTR register
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in Table 103.
3
FLR
Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over
from its maximum value to zero. The exact value at which the rollover occurs depends on the frame
list size. For example, if the frame list size, as programmed in FLS (bits 3 to 2) of the USBCMD
register, is 1024, the Frame Index register rolls over every time bit 13 of the FRINDEX register
toggles. Similarly, if the size is 512, the host controller sets this bit to logic 1 every time bit 12 of the
FRINDEX register toggles.
2
PCD
Port Change Detect: The host controller sets this bit to logic 1 when any port, where PO (bit 13 of
PORTSC) is cleared, changes to logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of
a J-K transition detected on a suspended port. This bit is allowed to be maintained in the auxiliary
power well. Alternatively, it is also acceptable that, on a D3-to-D0 transition of the EHCI host
controller device, this bit is loaded with the logical OR of all the PORTSC change bits, including
force port resume, overcurrent change, enable or disable change, and connect status change.
1
USBERR
INT
USB Error Interrupt: The host controller sets this bit when an error condition occurs because of
completing a USB transaction. For example, error counter underow. If the Transfer Descriptor (TD)
on which the error interrupt occurred also had its IOC bit set, both this bit and the USBINT bit are
set. For details, refer to
Enhanced Host Controller Interface Specication for Universal Serial Bus
Rev. 1.0.
0
USBINT
USB Interrupt: The host controller sets this bit on completing a USB transaction, which results in
the retirement of a TD that had its IOC bit set. The host controller also sets this bit when a short
packet is detected, that is, the actual number of bytes received was less than the expected number
of bytes. For details, refer to
Enhanced Host Controller Interface Specication for Universal Serial
Bus Rev. 1.0.
Table 102. USBSTS - USB Status register bit description …continued
Address: Content of the base address register + 24h
Bit
Symbol
Description
Table 103. USBINTR - USB Interrupt Enable register bit allocation
Address: Content of the base address register + 28h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
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