參數(shù)資料
型號(hào)： K4B4G0846B-MCF80
元件分類： DRAM
英文描述： 512M X 8 DDR DRAM, 0.3 ns, PBGA78
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
文件頁數(shù)： 23/59頁
文件大?。?/td> 1079K
代理商： K4B4G0846B-MCF80
Page 3 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
1.0 Ordering Information ................................................................................................................... 5
2.0 Key Features ................................................................................................................................ 5
3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6
3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package
.............................................................. 6
3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package
.............................................................. 7
3.3 FBGA Package Dimension (x4)
..................................................................................................... 8
3.4 FBGA Package Dimension (x8)
..................................................................................................... 9
4.0 Input/Output Functional Description ....................................................................................... 10
5.0 DDR3 SDRAM Addressing ........................................................................................................ 11
6.0 Absolute Maximum Ratings ...................................................................................................... 12
6.1 Absolute Maximum DC Ratings
................................................................................................... 12
6.2 DRAM Component Operating Temperature Range
......................................................................... 12
7.0 AC & DC Operation Conditions ................................................................................................ 12
7.1 Recommended DC operating Conditions (SSTL_1.5)
..................................................................... 12
8.0 AC & DC Input Measurement Levels ........................................................................................ 13
8.1 AC and DC Logic input levels for single-ended singnals
................................................................ 13
8.2 VREF Tolerances
....................................................................................................................... 14
8.3 AC and DC Logic Input Levels for Ditterential Signals
................................................................... 15
8.3.1 Differential signal definition
................................................................................................ 15
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
.............................. 15
8.3.3 Single-ended requirements for differential signals
................................................................. 16
8.4 Differential Input Cross Point Voltage
.......................................................................................... 17
8.5 Slew Rate Definition for Single Ended Input Signals
...................................................................... 17
8.6 Slew rate definition for Differential Input Signals
........................................................................... 17
9.0 AC and DC Output Measurement Levels ................................................................................. 18
9.1 Single Ended AC and DC Output Levels
....................................................................................... 18
9.2 Differential AC and DC Output Levels
.......................................................................................... 18
9.3 Single Ended Output Slew Rate
................................................................................................... 18
9.4 Differential Output Slew Rate
...................................................................................................... 19
9.5 Reference Load for AC Timing and Output Slew Rate
.................................................................... 19
9.6 Overshoot/Undershoot Specification
........................................................................................... 20
9.6.1 Address and Control Overshoot and Undershoot specifications
............................................. 20
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications
................................. 20
9.7 34 ohm Output Driver DC Electrical Characteristics
....................................................................... 21
9.7.1 Output Drive Temperature and Voltage sensitivity
................................................................. 22
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
............................................................... 22
9.8.1 ODT DC electrical characteristics
........................................................................................ 23
9.8.2 ODT Temperature and Voltage sensitivity
............................................................................. 24
Table Contents
相關(guān)PDF資料
PDF描述
K4E640411D-TC500 16M X 4 EDO DRAM, 50 ns, PDSO32
K4F640411C-TC500 16M X 4 FAST PAGE DRAM, 50 ns, PDSO32
K4F640412C-JC450 16M X 4 FAST PAGE DRAM, 45 ns, PDSO32
K4T1G044QC-ZCLE6 256M X 4 DDR DRAM, 0.45 ns, PBGA60
K4T56163QI-ZLD50 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4B4G0846B-MCH9 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDP 4Gb B-die DDR3 SDRAM Specification
K4B4G0846D-BCK0000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCH9000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK0000 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*