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Page 38 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
12.0 Input/Output Capacitance
[ Table 41 ] Input/Output Capacitance
Note :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary).
VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
TBD
pF
1,2,3
Input capacitance
(CK and CK)
CCK
TBD
pF
2,3
Input capacitance delta
(CK and CK)
CDCK
TBD
pF
2,3,4
Input capacitance
(All other input-only pins)
CI
TBDTBD
TBD
TBDTBD
pF
2,3,6
Input capacitance delta
(DQS and DQS)
CDDQS
TBD
pF
2,3,5
Input capacitance delta
(All control input-only pins)
CDI_CTRL
TBD
pF
2,3,7,8
Input capacitance delta
(all ADD and CMD input-onlypins)
CDI_ADD_CMD
TBD
pF
2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO
TBDTBD
TBD
TBDTBD
pF
2,3,11
Input/output capacitance of ZQ pin
CZQ
TBD
pF
2, 3, 12