參數(shù)資料
型號(hào)： K4B4G0846B-MCF80
元件分類(lèi)： DRAM
英文描述： 512M X 8 DDR DRAM, 0.3 ns, PBGA78
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
文件頁(yè)數(shù)： 33/59頁(yè)
文件大小： 1079K
代理商： K4B4G0846B-MCF80
Page 39 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
13.1 Clock specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK (avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
13.1.2 Definition for tCK (abs)
tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
13.1.4 Definition for note for tJIT(per), tJIT(per,Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for note for tJIT(cc), tJIT(cc,Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
N
j=1
tCKj
N
N=200
∑
N
j=1
tCHj
N x tCK(avg)
N=200
N
j=1
tCLj
N x tCK(avg)
N=200
∑
相關(guān)PDF資料
PDF描述
K4E640411D-TC500 16M X 4 EDO DRAM, 50 ns, PDSO32
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K4F640412C-JC450 16M X 4 FAST PAGE DRAM, 45 ns, PDSO32
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4B4G0846B-MCH9 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:DDP 4Gb B-die DDR3 SDRAM Specification
K4B4G0846D-BCK0000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCH9000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK0000 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays
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