參數(shù)資料
型號: K4B4G0846B-MCF80
元件分類: DRAM
英文描述: 512M X 8 DDR DRAM, 0.3 ns, PBGA78
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
文件頁數(shù): 35/59頁
文件大?。?/td> 1079K
代理商: K4B4G0846B-MCF80
Page 40 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
13.2 Refresh Parameters by Device Density
[ Table 42 ] Refresh parameters by device density
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 43 ] DDR3-800 Speed Bins
[ Table 44 ] DDR3-1066 Speed Bins
Parameter
Symbol
1Gb
2Gb
4Gb
8Gb
Units
Note
All Bank Refresh to active/refresh cmd time
tRFC
110
160
300
350
ns
Average periodic refresh interval
tREFI
0
°C ≤ TCASE ≤ 85°C
7.8
s
85
°C < TCASE ≤ 95°C
3.9
s
1
Speed
DDR3-800
Units
Note
CL-nRCD-nRP
6 - 6 - 6
Parameter
Symbol
min
max
Intermal read command to first data
tAA
15
20
ns
ACT to internal read or write delay time
tRCD
15
-
ns
PRE command period
tRP
15
-
ns
ACT to ACT or REF command period
tRC
52.5
-
ns
ACT to PRE command period
tRAS
37.5
9*tREFI
ns
8
CL = 6 / CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3
Supported CL Settings
6
nCK
Supported CWL Settings
5
nCK
Speed
DDR3-1066
Units
Note
CL-nRCD-nRP
7 - 7 - 7
Parameter
Symbol
min
max
Intermal read command to first data
tAA
13.125
20
ns
ACT to internal read or write delay time
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
50.625
-
ns
ACT to PRE command period
tRAS
37.5
9*tREFI
ns
8
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,6
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3,4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
<2.5
ns
1,2,3
Supported CL Settings
6,7,8
nCK
Supported CWL Settings
5,6
nCK
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