參數(shù)資料
型號(hào)： K4B4G0846B-MCF80
元件分類(lèi)： DRAM
英文描述： 512M X 8 DDR DRAM, 0.3 ns, PBGA78
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
文件頁(yè)數(shù)： 6/59頁(yè)
文件大?。?/td> 1079K
代理商： K4B4G0846B-MCF80
Page 14 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in table 7. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
voltage
VDD
VSS
time
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4B4G0846B-MCH9 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:DDP 4Gb B-die DDR3 SDRAM Specification
K4B4G0846D-BCK0000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCH9000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK0000 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays
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