參數(shù)資料
型號: LPC3250FET296,551
廠商: NXP Semiconductors
文件頁數(shù): 10/57頁
文件大小: 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標準包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,電機控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
配用: 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱: 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
18 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
P0[2]/
I2S0RX_SDA/
LCDVD[4]
M17
VDD_IOA
I/O
Port 0 GPIO bit 2
I/O
I2S0 receive data
I/O
LCD data bit 4 (LPC3230 and LPC3250 only)
P0[3]/
I2S0RX_CLK/
LCDVD[5]
M18
VDD_IOA
I/O
Port 0 GPIO bit 3
I/O
I2S0 receive clock
I/O
LCD data bit 5 (LPC3230 and LPC3250 only)
P0[4]/
I2S0RX_WS/
LCDVD[6]
L15
VDD_IOA
I/O
Port 0 GPIO bit 4
I/O
I2S0 receive word select
I/O
LCD data bit 6 (LPC3230 and LPC3250 only)
P0[5]/
I2S0TX_SDA/
LCDVD[7]
L16
VDD_IOA
I/O
Port 0 GPIO bit 5
I/O
I2S0 transmit data
I/O
LCD data bit 7 (LPC3230 and LPC3250 only)
P0[6]/
I2S0TX_CLK/
LCDVD[12]
L17
VDD_IOA
I/O
Port 0 GPIO bit 6
I/O
I2S0 transmit clock
I/O
LCD data bit 12 (LPC3230 and LPC3250 only)
P0[7]/
I2S0TX_WS/
LCDVD[13]
L18
VDD_IOA
I/O
Port 0 GPIO bit 7
I/O
I2S0 transmit word select
I/O
LCD data bit 13 (LPC3230 and LPC3250 only)
PLL397_LOOP
R14
VDD_PLL397
analog filter
PLL397 loop filter
(for external components)
PWM_OUT1/
LCDVD[16]
D14
VDD_IOD
O
PWM1 out
O
LCD data bit 16 (LPC3230 and LPC3250 only)
PWM_OUT2/INTSTAT/
LCDVD[19]
D15
VDD_IOD
O
PWM2 output/internal interrupt status[1]
O
LCD data bit 19 (LPC3230 and LPC3250 only)
RESET
M14
VDD_RTC
I
Reset input, active LOW
RESOUT
G4
VDD_IOC
O
Reset out. Reflects external and WDT reset
RTCX_IN
P16
VDD_RTC
analog in
RTC oscillator input
RTCX_OUT
P17
VDD_RTC
analog out
RTC oscillator output
SPI1_CLK/
SCK0
C9
VDD_IOD
O
SPI1 clock out
O
SSP0 clock out
SPI1_DATIN/
MISO0/
GPI_25/
MCI1
C10
VDD_IOD
I/O
SPI1 data in
I/O
SSP0 MISO
I/O
General purpose input bit 25
I
Motor control channel 1 input
SPI1_DATIO/
MOSI0/
MCI2
B9
VDD_IOD
I/O
SPI1 data out (and optional input)
I/O
SSP0 MOSI
I
Motor control channel 2 input
SPI2_CLK/
SCK1/
LCDVD[23]
B10
VDD_IOD
I/O
SPI2 clock out
I/O
SSP1 clock out
I/O
LCD data bit 23 (LPC3230 and LPC3250 only)
Table 4.
Pin description …continued
Symbol
Pin
Power supply
domain
Type
Description
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