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參數(shù)資料
| 型號(hào)： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 33/57頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲(chǔ)器類(lèi)型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤(pán) |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱(chēng)： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
39 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are
only available when the controller is configured as a Master/Slave device and is operating
in a multi-master environment. Separate TX FIFOs are needed in a multi-master because
a controller might have a message queued for transmission when an external master
addresses it to be come a slave-transmitter, a second source of data is needed.
Note that the I2C clock must be enabled in the I2CCLK_CTRL register before using the
I2C. The I2C clock can be disabled between communications, if used as a single master
I2C-bus interface, software has full control of when I2C communication is taking place on
the bus.
7.8.4.1
Features
The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in
Single-master, Multi-master or Slave modes.
Programmable clock to allow adjustment of I2C-bus transfer rates.
Bidirectional data transfer.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
7.8.5 I2S-bus audio controller
The I2S-bus provides a standard communication interface for digital audio applications
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. Each I2S connection can act as a master or a slave. The
master connection determines the frequency of the clock line and all other slaves are
driven by this clock source. The two I2S-bus interfaces on the LPC3220/30/40/50 provides
a separate transmit and receive channel, providing a total of two transmit channels and
two receive channels. Each I2S channel supports monaural or stereo formatted data.
7.8.5.1
Features
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz,
32 kHz, 44.1 kHz, 48 kHz, 96 kHz).
Word select period can be configured in master mode (separately for I2S input and
output).
Two eight-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop, and mute options separately for I2S input and I2S output.
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