參數(shù)資料
型號: LPC3250FET296,551
廠商: NXP Semiconductors
文件頁數(shù): 3/57頁
文件大?。?/td> 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,電機(jī)控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
配用: 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱: 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
11 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
EMC_A[15]/P1[15]
L1
VDD_EMC
I/O
EMC address bit 15
I/O
Port 1 GPIO bit 15
EMC_A[16]/P1[16]
K3
VDD_EMC
I/O
EMC address bit 16
I/O
Port 1 GPIO bit 16
EMC_A[17]/P1[17]
K4
VDD_EMC
I/O
EMC address bit 17
I/O
Port 1 GPIO bit 17
EMC_A[18]/P1[18]
K2
VDD_EMC
I/O
EMC address bit 18
I/O
Port 1 GPIO bit 18
EMC_A[19]/P1[19]
K1
VDD_EMC
I/O
EMC address bit 19
I/O
Port 1 GPIO bit 19
EMC_A[20]/P1[20]
J1
VDD_EMC
I/O
EMC address bit 20
I/O
Port 1 GPIO bit 20
EMC_A[21]/P1[21]
J2
VDD_EMC
I/O
EMC address bit 21
I/O
Port 1 GPIO bit 21
EMC_A[22]/P1[22]
J3
VDD_EMC
I/O
EMC address bit 22
I/O
Port 1 GPIO bit 22
EMC_A[23]/P1[23]
J4
VDD_EMC
I/O
EMC address bit 23
I/O
Port 1 GPIO bit 23
EMC_BLS[0]
U14
VDD_EMC
O
Static memory byte lane 0 select
EMC_BLS[1]
T13
VDD_EMC
O
Static memory byte lane 1 select
EMC_BLS[2]
R12
VDD_EMC
O
Static memory byte lane 2 select
EMC_BLS[3]
P12
VDD_EMC
O
Static memory byte lane 3 select
EMC_CAS
R5
VDD_EMC
O
SDRAM column address strobe out, active LOW
EMC_CKE0
U3
VDD_EMC
O
Clock enable out for SDRAM bank 0
EMC_CKE1
L2
VDD_EMC
O
Clock enable out for SDRAM bank 1
EMC_CLK
T3
VDD_EMC
O
SDRAM clock out
EMC_CLKIN
T4
VDD_EMC
I
SDRAM clock feedback
EMC_CS0
U13
VDD_EMC
O
EMC static memory chip select 0
EMC_CS1
R11
VDD_EMC
O
EMC static memory chip select 1
EMC_CS2
T12
VDD_EMC
O
EMC static memory chip select 2
EMC_CS3
V15
VDD_EMC
O
EMC static memory chip select 3
EMC_D[0]
U4
VDD_EMC
I/O: BK
EMC data bit 0
EMC_D[1]
R7
VDD_EMC
I/O: BK
EMC data bit 1
EMC_D[2]
T5
VDD_EMC
I/O: BK
EMC data bit 2
EMC_D[3]
U5
VDD_EMC
I/O: BK
EMC data bit 3
EMC_D[4]
V3
VDD_EMC
I/O: BK
EMC data bit 4
EMC_D[5]
V4
VDD_EMC
I/O: BK
EMC data bit 5
EMC_D[6]
T6
VDD_EMC
I/O: BK
EMC data bit 6
EMC_D[7]
R8
VDD_EMC
I/O: BK
EMC data bit 7
EMC_D[8]
V5
VDD_EMC
I/O: BK
EMC data bit 8
Table 4.
Pin description …continued
Symbol
Pin
Power supply
domain
Type
Description
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