參數(shù)資料
型號： LPC3250FET296,551
廠商： NXP Semiconductors
文件頁數(shù)： 30/57頁
文件大?。?/td> 0K
描述： IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品： LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝： 126
系列： LPC3200
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 266MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲器類型： ROMless
RAM 容量： 256K x 8
電壓 - 電源 (Vcc/Vdd)： 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 296-TFBGA
包裝： 托盤
配用： 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱： 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
36 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
output to be used directly. The maximum PLL output frequency supported by the CPU is
266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock
has strict requirements for nominal frequency (500 ppm) and jitter (500 ps).
7.7.4.4
Power control modes
The LPC3220/30/40/50 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct Run mode,
and Stop mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at
up to 133 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
7.7.4.5
Reset
Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse
with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to
guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the
oscillator to start up and stabilize after VDD reaches operational voltage. An internal reset
with a minimum duration of 10 clock pulses will also be applied if the watchdog timer
generates an internal device reset.
The RESET pin is located in the RTC power domain. This means that the RTC power
must be present for an external reset to have any effect. The RTC power domain
nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95 V.
7.8
Communication peripheral interfaces
In addition to the Ethernet MAC and USB interfaces there are many more serial
communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of
the serial communication interfaces:
Seven UARTs; four standard UARTs and three high-speed UARTs
Two SPI serial I/O controllers
Two SSP serial I/O controllers
Two I2C serial I/O controllers
Two I2S audio controllers
A short functional description of each of these peripherals is provided in the following
sections.
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