參數(shù)資料
型號(hào): LPC3250FET296,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 53/57頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,電機(jī)控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲(chǔ)器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
配用: 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱: 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
57 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11. Dynamic characteristics
11.1 Clocking and I/O port pins
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
After supply voltages are stable
[3]
Supplied by an external crystal.
11.2 Static memory controller
Table 11.
Dynamic characteristics
Tamb = 40 C to +85 C, unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset
tw(RESET)ext
external RESET pulse width
-
ms
External clock
fext
external clock frequency
[3] 113
20
MHz
Port pins
tr
rise time
-
5
-
ns
tf
fall time
-
5
-
ns
Table 12.
Dynamic characteristics: static external memory interface
CL =25 pF, Tamb =20 C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V.
Symbol
Parameter
Notes Min
Typ
Max
Unit
Common to read and write cycles
TCLCL
clock cycle time
[1] 7.5
9.6
-
ns
tCSLAV
CS LOW to address valid time
-
0
-
ns
Read cycle parameters
tOELAV
OE LOW to address valid time
WAITOEN T
CLCL
-ns
tBLSLAV
BLS LOW to address valid time
WAITOEN T
CLCL
-ns
tCSLOEL
CS LOW to OE LOW time
-
0 + WAITOEN
T
CLCL
-ns
tCSLBLSL
CS LOW to BLS LOW time
0 + WAITOEN
T
CLCL
-ns
tOELOEH
OE LOW to OE HIGH time
[2][3] -(WAITRD
WAITOEN + 1) T
CLCL
-ns
tBLSLBLSH
BLS LOW to BLS HIGH time
[2][3] -(WAITRD
WAITOEN + 1) T
CLCL
-ns
tsu(DQ)
data input/output set-up time
[6] -8.4
-
ns
th(DQ)
data input/output hold time
-
ns
tCSHOEH
CS HIGH to OE HIGH time
-
0
-
ns
tCSHBLSH
CS HIGH to BLS HIGH time
-
0
-
ns
tOEHANV
OE HIGH to address invalid time
-
1
T
CLCL
-ns
tBLSHANV
BLS HIGH to address invalid time
-
1
T
CLCL
-ns
Write cycle parameters
tCSLDV
CS LOW to data valid time
-
0
-
ns
tCSLWEL
CS LOW to WE LOW time
[4] -(WAITWEN + 1)
T
CLCL
-ns
tCSLBLSL
CS LOW to BLS LOW time
[4] -(WAITWEN + 1)
T
CLCL
-ns
tWELDV
WE LOW to data valid time
(WAITWEN + 1) T
CLCL
-ns
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