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參數(shù)資料
| 型號(hào)： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 37/57頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲(chǔ)器類(lèi)型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤(pán) |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱(chēng)： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
42 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Two 32-bit match registers are readable and writable by the processor. A match will result
in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be
triggered by a match event and cause an external power supply to turn on all of the
operating voltages, as a way to startup after power has been removed.
The RTC block is implemented in a separate voltage domain. The block is supplied via a
separate supply pin from a battery or other power source.
The RTC block also contains 32 words (128 bytes) of very low voltage SRAM. This SRAM
is able to hold its contents down to the minimum RTC operating voltage.
7.9.4.1
Features
Measures the passage of time in seconds.
32-bit up and down seconds counters.
Ultra-low power design to support battery powered systems.
Dedicated 32 kHz oscillator.
An output pin is included to assist in waking up when the chip has had power removed
to all functions except the RTC.
Two 32-bit match registers with interrupt option.
32 words (128 bytes) of very low voltage SRAM.
The RTC and battery RAM power have an independent power domain and dedicated
supply pins, which can be powered from a battery or power supply.
Remark: The LPC3220/30/40/50 will run at voltages down to 0.9 V at frequencies below
14 MHz. However, the ARM core cannot access the RTC registers and battery RAM when
the core supply voltage is at 0.9 V and the RTC supply is at 1.2 V.
7.9.5 Enhanced 32-bit timers/external event counters
The LPC3220/30/40/50 includes six 32-bit Timer/Counters. The Timer/Counter is
designed to count cycles of the system derived clock or an externally-supplied clock. It
can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. The Timer/Counter also includes four capture inputs to trap
the timer value when an input signal transitions, optionally generating an interrupt.
7.9.5.1
Features
A 32-bit Timer/Counter with a programmable 32-bit pre-scaler.
Counter or Timer operation.
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– continuous operation with optional interrupt generation on match
– stop timer on match with optional interrupt generation
– reset timer on match with optional interrupt generation
Up to four external outputs corresponding to match registers, with the following
capabilities:
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